DE60041319D1 - Feinkörnige nutzerprogrammierbare gatterfeldarchitektur und schaltung - Google Patents

Feinkörnige nutzerprogrammierbare gatterfeldarchitektur und schaltung

Info

Publication number
DE60041319D1
DE60041319D1 DE60041319T DE60041319T DE60041319D1 DE 60041319 D1 DE60041319 D1 DE 60041319D1 DE 60041319 T DE60041319 T DE 60041319T DE 60041319 T DE60041319 T DE 60041319T DE 60041319 D1 DE60041319 D1 DE 60041319D1
Authority
DE
Germany
Prior art keywords
finest
circuit
programmable gate
gate frame
user programmable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60041319T
Other languages
English (en)
Inventor
Ronald L Cline
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Application granted granted Critical
Publication of DE60041319D1 publication Critical patent/DE60041319D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
DE60041319T 1999-07-16 2000-07-12 Feinkörnige nutzerprogrammierbare gatterfeldarchitektur und schaltung Expired - Lifetime DE60041319D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/354,607 US6294926B1 (en) 1999-07-16 1999-07-16 Very fine-grain field programmable gate array architecture and circuitry
PCT/EP2000/006628 WO2001006657A1 (en) 1999-07-16 2000-07-12 Very fine grain field programmable gate array architecture and circuitry

Publications (1)

Publication Number Publication Date
DE60041319D1 true DE60041319D1 (de) 2009-02-26

Family

ID=23394120

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60041319T Expired - Lifetime DE60041319D1 (de) 1999-07-16 2000-07-12 Feinkörnige nutzerprogrammierbare gatterfeldarchitektur und schaltung

Country Status (8)

Country Link
US (2) US6294926B1 (de)
EP (1) EP1114514B1 (de)
JP (1) JP2003505911A (de)
KR (1) KR100735168B1 (de)
CN (1) CN1181617C (de)
DE (1) DE60041319D1 (de)
TW (1) TW567669B (de)
WO (1) WO2001006657A1 (de)

Families Citing this family (15)

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Publication number Priority date Publication date Assignee Title
US6567290B2 (en) * 2000-07-05 2003-05-20 Mosaic Systems, Inc. High-speed low-power semiconductor memory architecture
SE0102199D0 (sv) * 2001-06-20 2001-06-20 Ericsson Telefon Ab L M Upgrading field programmable gate arrays over datacommunication networks
US6747480B1 (en) * 2002-07-12 2004-06-08 Altera Corporation Programmable logic devices with bidirect ional cascades
US6886152B1 (en) * 2002-08-09 2005-04-26 Xilinx, Inc. Delay optimization in signal routing
US7243329B2 (en) * 2004-07-02 2007-07-10 Altera Corporation Application-specific integrated circuit equivalents of programmable logic and associated methods
US8046729B1 (en) 2004-11-24 2011-10-25 Altera Corporation Method and apparatus for composing and decomposing low-skew networks
JP2009507414A (ja) * 2005-09-05 2009-02-19 エヌエックスピー ビー ヴィ 半導体集積回路用論理モジュール
JP2007243671A (ja) * 2006-03-09 2007-09-20 Kddi Corp 論理プログラマブルデバイス保護回路
US8510239B2 (en) * 2010-10-29 2013-08-13 International Business Machines Corporation Compact cognitive synaptic computing circuits with crossbar arrays spatially in a staggered pattern
CN103064328B (zh) * 2012-12-15 2015-05-20 中国科学院近代物理研究所 数字脉冲电源同步定时触发系统
US9164794B2 (en) * 2013-08-20 2015-10-20 Netronome Systems, Inc. Hardware prefix reduction circuit
CN105634468B (zh) * 2014-10-30 2018-11-06 京微雅格（北京）科技有限公司 一种fpga的布线方法和宏单元
US9667314B1 (en) * 2015-12-15 2017-05-30 Altera Corporation Programmable repeater circuits and methods
US10216422B2 (en) 2016-11-24 2019-02-26 Samsung Electronics Co., Ltd. Storage device including nonvolatile memory device and access method for nonvolatile memory device
US11507806B2 (en) * 2017-09-08 2022-11-22 Rohit Seth Parallel neural processor for Artificial Intelligence

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5019736A (en) 1986-11-07 1991-05-28 Concurrent Logic, Inc. Programmable logic cell and array
US5051917A (en) * 1987-02-24 1991-09-24 International Business Machines Corporation Method of combining gate array and standard cell circuits on a common semiconductor chip
GB8828828D0 (en) 1988-12-09 1989-01-18 Pilkington Micro Electronics Semiconductor integrated circuit
US5203005A (en) 1989-05-02 1993-04-13 Horst Robert W Cell structure for linear array wafer scale integration architecture with capability to open boundary i/o bus without neighbor acknowledgement
US5055718A (en) 1990-05-11 1991-10-08 Actel Corporation Logic module with configurable combinational and sequential blocks
GB9223226D0 (en) 1992-11-05 1992-12-16 Algotronix Ltd Improved configurable cellular array (cal ii)
US5682107A (en) * 1994-04-01 1997-10-28 Xilinx, Inc. FPGA architecture with repeatable tiles including routing matrices and logic matrices
US5442306A (en) * 1994-09-09 1995-08-15 At&T Corp. Field programmable gate array using look-up tables, multiplexers and decoders
US5872380A (en) * 1994-11-02 1999-02-16 Lsi Logic Corporation Hexagonal sense cell architecture
US5898318A (en) * 1994-11-04 1999-04-27 Altera Corporation Programmable logic array integrated circuits with enhanced cascade
US5537057A (en) * 1995-02-14 1996-07-16 Altera Corporation Programmable logic array device with grouped logic regions and three types of conductors
US5594363A (en) 1995-04-07 1997-01-14 Zycad Corporation Logic cell and routing architecture in a field programmable gate array
JP3118630B2 (ja) * 1995-09-22 2000-12-18 株式会社日立製作所 石炭ガス化炉
US5720031A (en) 1995-12-04 1998-02-17 Micron Technology, Inc. Method and apparatus for testing memory devices and displaying results of such tests
US5734582A (en) * 1995-12-12 1998-03-31 International Business Machines Corporation Method and system for layout and schematic generation for heterogeneous arrays
US6107822A (en) * 1996-04-09 2000-08-22 Altera Corporation Logic element for a programmable logic integrated circuit
US5781032A (en) * 1996-09-09 1998-07-14 International Business Machines Corporation Programmable inverter circuit used in a programmable logic cell
US6005410A (en) * 1996-12-05 1999-12-21 International Business Machines Corporation Interconnect structure between heterogeneous core regions in a programmable array
US5880598A (en) * 1997-01-10 1999-03-09 Xilinx, Inc. Tile-based modular routing resources for high density programmable logic device
US5889411A (en) * 1997-02-26 1999-03-30 Xilinx, Inc. FPGA having logic element carry chains capable of generating wide XOR functions
US6084429A (en) * 1998-04-24 2000-07-04 Xilinx, Inc. PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays
US6346826B1 (en) * 1998-12-23 2002-02-12 Integrated Logic Systems, Inc Programmable gate array device
US6359468B1 (en) * 1999-03-04 2002-03-19 Altera Corporation Programmable logic device with carry look-ahead

Also Published As

Publication number Publication date
US6525561B2 (en) 2003-02-25
TW567669B (en) 2003-12-21
JP2003505911A (ja) 2003-02-12
CN1321359A (zh) 2001-11-07
US6294926B1 (en) 2001-09-25
US20020011868A1 (en) 2002-01-31
KR20010075126A (ko) 2001-08-09
EP1114514A1 (de) 2001-07-11
KR100735168B1 (ko) 2007-07-03
CN1181617C (zh) 2004-12-22
EP1114514B1 (de) 2009-01-07
WO2001006657A1 (en) 2001-01-25

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