DE60043212D1 - Erzeugung eines Addressenübergangssignals (ATD) für eine synchrone Speicheranordnung - Google Patents

Erzeugung eines Addressenübergangssignals (ATD) für eine synchrone Speicheranordnung

Info

Publication number
DE60043212D1
DE60043212D1 DE60043212T DE60043212T DE60043212D1 DE 60043212 D1 DE60043212 D1 DE 60043212D1 DE 60043212 T DE60043212 T DE 60043212T DE 60043212 T DE60043212 T DE 60043212T DE 60043212 D1 DE60043212 D1 DE 60043212D1
Authority
DE
Germany
Prior art keywords
atd
generation
memory device
address transition
transition signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60043212T
Other languages
English (en)
Inventor
Fabrizio Campanale
Salvatore Nicosia
Francesco Tomaiuolo
Ambroggi Luca Giuseppe De
Promod Kumar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE60043212D1 publication Critical patent/DE60043212D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
DE60043212T 2000-01-31 2000-04-27 Erzeugung eines Addressenübergangssignals (ATD) für eine synchrone Speicheranordnung Expired - Lifetime DE60043212D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP00830068A EP1122734B1 (de) 2000-01-31 2000-01-31 Verschachtelter Burst-Speicher mit Burst-Zugriff bei synchronen Lesezyklen, wobei die beiden untergeordneten Speicherfelder unabhängig lesbar sind mit wahlfreiem Zugriff während asynchroner Lesezyklen

Publications (1)

Publication Number Publication Date
DE60043212D1 true DE60043212D1 (de) 2009-12-10

Family

ID=8175158

Family Applications (3)

Application Number Title Priority Date Filing Date
DE60019081T Expired - Lifetime DE60019081D1 (de) 2000-01-31 2000-01-31 Verschachtelter Burst-Speicher mit Burst-Zugriff bei synchronen Lesezyklen, wobei die beiden untergeordneten Speicherfelder unabhängig lesbar sind mit wahlfreiem Zugriff während asynchroner Lesezyklen
DE60044895T Expired - Lifetime DE60044895D1 (de) 2000-01-31 2000-04-17 Verschachtelter Datenpfad und Ausgabesteuerungsarchitektur für einen verschachtelten Speicher sowie Impulsgeber zum Ausgeben von gelesenen Daten
DE60043212T Expired - Lifetime DE60043212D1 (de) 2000-01-31 2000-04-27 Erzeugung eines Addressenübergangssignals (ATD) für eine synchrone Speicheranordnung

Family Applications Before (2)

Application Number Title Priority Date Filing Date
DE60019081T Expired - Lifetime DE60019081D1 (de) 2000-01-31 2000-01-31 Verschachtelter Burst-Speicher mit Burst-Zugriff bei synchronen Lesezyklen, wobei die beiden untergeordneten Speicherfelder unabhängig lesbar sind mit wahlfreiem Zugriff während asynchroner Lesezyklen
DE60044895T Expired - Lifetime DE60044895D1 (de) 2000-01-31 2000-04-17 Verschachtelter Datenpfad und Ausgabesteuerungsarchitektur für einen verschachtelten Speicher sowie Impulsgeber zum Ausgeben von gelesenen Daten

Country Status (4)

Country Link
US (1) US6587913B2 (de)
EP (1) EP1122734B1 (de)
JP (1) JP3472556B2 (de)
DE (3) DE60019081D1 (de)

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US7143185B1 (en) * 2000-08-29 2006-11-28 Advanced Micro Devices, Inc. Method and apparatus for accessing external memories
EP1199723B1 (de) * 2000-10-18 2008-12-31 STMicroelectronics S.r.l. Verschachtelte Speichereinrichtung mit willkürlichem und sequentiellem Zugriff
US6445624B1 (en) * 2001-02-23 2002-09-03 Micron Technology, Inc. Method of synchronizing read timing in a high speed memory system
US7085186B2 (en) * 2001-04-05 2006-08-01 Purple Mountain Server Llc Method for hiding a refresh in a pseudo-static memory
WO2004006103A1 (en) * 2002-07-09 2004-01-15 Globespanvirata Incorporated Method and system for improving access latency of multiple bank devices
FR2864730B1 (fr) * 2003-12-26 2006-03-17 Temento Systems Dispositif de memorisation
US7355470B2 (en) 2006-04-24 2008-04-08 Parkervision, Inc. Systems and methods of RF power transmission, modulation, and amplification, including embodiments for amplifier class transitioning
US7327803B2 (en) 2004-10-22 2008-02-05 Parkervision, Inc. Systems and methods for vector power amplification
WO2006064423A1 (en) * 2004-12-13 2006-06-22 Koninklijke Philips Electronics N.V. Reception of a signal transmitted over a transmission link comprising coded channels
US7911272B2 (en) 2007-06-19 2011-03-22 Parkervision, Inc. Systems and methods of RF power transmission, modulation, and amplification, including blended control embodiments
US8334722B2 (en) 2007-06-28 2012-12-18 Parkervision, Inc. Systems and methods of RF power transmission, modulation and amplification
US9106316B2 (en) 2005-10-24 2015-08-11 Parkervision, Inc. Systems and methods of RF power transmission, modulation, and amplification
US7441949B2 (en) * 2005-12-16 2008-10-28 Micron Technology, Inc. System and method for providing temperature data from a memory device having a temperature sensor
US8031804B2 (en) 2006-04-24 2011-10-04 Parkervision, Inc. Systems and methods of RF tower transmission, modulation, and amplification, including embodiments for compensating for waveform distortion
US7937106B2 (en) 2006-04-24 2011-05-03 ParkerVision, Inc, Systems and methods of RF power transmission, modulation, and amplification, including architectural embodiments of same
US8315336B2 (en) 2007-05-18 2012-11-20 Parkervision, Inc. Systems and methods of RF power transmission, modulation, and amplification, including a switching stage embodiment
JP2008077418A (ja) * 2006-09-21 2008-04-03 Sanyo Electric Co Ltd メモリアクセス装置
US7483334B2 (en) * 2006-09-26 2009-01-27 Micron Technology, Inc. Interleaved input signal path for multiplexed input
WO2008076737A2 (en) * 2006-12-13 2008-06-26 Cypress Semiconductor Corp. Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock domain
WO2008156800A1 (en) 2007-06-19 2008-12-24 Parkervision, Inc. Combiner-less multiple input single output (miso) amplification with blended control
US7930121B2 (en) * 2008-07-03 2011-04-19 Texas Instrument Incorporated Method and apparatus for synchronizing time stamps
US8144515B2 (en) 2009-07-23 2012-03-27 Stec, Inc. Interleaved flash storage system and method
KR101201857B1 (ko) 2010-08-27 2012-11-15 에스케이하이닉스 주식회사 반도체 메모리 장치 및 반도체 메모리 장치의 데이터 읽기방법
EP2695294A1 (de) 2011-04-08 2014-02-12 Parkervision, Inc. System und verfahren zur hf-leistungsübertragung, -modulation und -verstärkung
EP2715867A4 (de) 2011-06-02 2014-12-17 Parkervision Inc Antennensteuerung
US9767058B2 (en) * 2011-11-17 2017-09-19 Futurewei Technologies, Inc. Method and apparatus for scalable low latency solid state drive interface
CN106415435B (zh) 2013-09-17 2020-08-11 帕克维辛股份有限公司 用于呈现信息承载时间函数的方法、装置和系统
US9772852B2 (en) 2015-04-23 2017-09-26 Google Inc. Energy efficient processor core architecture for image processor
JP6274589B1 (ja) * 2016-09-28 2018-02-07 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置および連続読出し方法
US11226909B2 (en) 2018-08-24 2022-01-18 Rambus Inc. DRAM interface mode with interruptible internal transfer operation
CN114417768B (zh) * 2022-03-29 2022-07-22 南京金阵微电子技术有限公司 一种以太网芯片的数模混合仿真方法及系统

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EP1122735B1 (de) * 2000-01-31 2010-09-01 STMicroelectronics Srl Verschachtelter Datenpfad und Ausgabesteuerungsarchitektur für einen verschachtelten Speicher sowie Impulsgeber zum Ausgeben von gelesenen Daten

Also Published As

Publication number Publication date
DE60044895D1 (de) 2010-10-14
EP1122734A1 (de) 2001-08-08
US20010033245A1 (en) 2001-10-25
JP3472556B2 (ja) 2003-12-02
EP1122734B1 (de) 2005-03-30
DE60019081D1 (de) 2005-05-04
US6587913B2 (en) 2003-07-01
JP2001243778A (ja) 2001-09-07

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