DE60129793D1 - Verfahren zum transfer und stapeln von halbleiterbausteinen - Google Patents

Verfahren zum transfer und stapeln von halbleiterbausteinen

Info

Publication number
DE60129793D1
DE60129793D1 DE60129793T DE60129793T DE60129793D1 DE 60129793 D1 DE60129793 D1 DE 60129793D1 DE 60129793 T DE60129793 T DE 60129793T DE 60129793 T DE60129793 T DE 60129793T DE 60129793 D1 DE60129793 D1 DE 60129793D1
Authority
DE
Germany
Prior art keywords
transfering
semiconductor components
stacking semiconductor
stacking
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60129793T
Other languages
English (en)
Other versions
DE60129793T2 (de
Inventor
Staf Borghs
Eric Beyne
Raf Vandersmissen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Umicore NV SA
Interuniversitair Microelektronica Centrum vzw IMEC
Original Assignee
Umicore NV SA
Interuniversitair Microelektronica Centrum vzw IMEC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Umicore NV SA, Interuniversitair Microelektronica Centrum vzw IMEC filed Critical Umicore NV SA
Application granted granted Critical
Publication of DE60129793D1 publication Critical patent/DE60129793D1/de
Publication of DE60129793T2 publication Critical patent/DE60129793T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
DE60129793T 2000-01-28 2001-01-29 Verfahren zum transfer und stapeln von halbleiterbausteinen Expired - Lifetime DE60129793T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17899400P 2000-01-28 2000-01-28
US178994P 2000-01-28
PCT/BE2001/000014 WO2001056079A2 (en) 2000-01-28 2001-01-29 A method for transferring and stacking of semiconductor devices

Publications (2)

Publication Number Publication Date
DE60129793D1 true DE60129793D1 (de) 2007-09-20
DE60129793T2 DE60129793T2 (de) 2008-04-30

Family

ID=22654784

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60129793T Expired - Lifetime DE60129793T2 (de) 2000-01-28 2001-01-29 Verfahren zum transfer und stapeln von halbleiterbausteinen

Country Status (6)

Country Link
US (2) US6576505B2 (de)
EP (1) EP1252654B1 (de)
JP (1) JP5022549B2 (de)
AU (1) AU2001229896A1 (de)
DE (1) DE60129793T2 (de)
WO (1) WO2001056079A2 (de)

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US10361802B1 (en) 1999-02-01 2019-07-23 Blanding Hovenweep, Llc Adaptive pattern recognition based control system and method
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
US6696765B2 (en) * 2001-11-19 2004-02-24 Hitachi, Ltd. Multi-chip module
TWI288435B (en) * 2000-11-21 2007-10-11 Matsushita Electric Ind Co Ltd Semiconductor device and equipment for communication system
EP1353170A3 (de) * 2002-03-28 2004-02-04 Interuniversitair Micro-Elektronica Centrum (IMEC) Sensor in Form eines Feldeffekttransistors
EP1348951A1 (de) * 2002-03-29 2003-10-01 Interuniversitair Micro-Elektronica Centrum Sensor in Form eines durch Moleküle gesteuerter Feldeffekttransistors mit zwei Gates
WO2005029185A2 (en) * 2003-09-16 2005-03-31 Matsushita Electric Industrial Co., Ltd. Led lighting source and led lighting apparatus
JP4241575B2 (ja) * 2004-11-05 2009-03-18 日立電線株式会社 小型アンテナ
EP1739736A1 (de) 2005-06-30 2007-01-03 Interuniversitair Microelektronica Centrum ( Imec) Verfahren zur Herstellung einer Halbleiteranordnung
US7236408B2 (en) * 2005-07-19 2007-06-26 International Business Machines Corporation Electronic circuit having variable biasing
CN101207972B (zh) * 2006-12-22 2010-05-19 鸿富锦精密工业（深圳）有限公司 一种电路板及使用其的感光装置
TWI351764B (en) * 2007-04-03 2011-11-01 Au Optronics Corp Pixel structure and method for forming the same
US20080296708A1 (en) * 2007-05-31 2008-12-04 General Electric Company Integrated sensor arrays and method for making and using such arrays
US7696062B2 (en) 2007-07-25 2010-04-13 Northrop Grumman Systems Corporation Method of batch integration of low dielectric substrates with MMICs
US8290325B2 (en) * 2008-06-30 2012-10-16 Intel Corporation Waveguide photodetector device and manufacturing method thereof
US20100148153A1 (en) * 2008-12-16 2010-06-17 Hudait Mantu K Group III-V devices with delta-doped layer under channel region
JP5635759B2 (ja) * 2009-10-15 2014-12-03 学校法人慶應義塾 積層半導体集積回路装置
US8313966B2 (en) * 2010-01-04 2012-11-20 The Royal Institution For The Advancement Of Learning/Mcgill University Method for fabricating optical semiconductor tubes and devices thereof
JP2013131650A (ja) * 2011-12-21 2013-07-04 Fujitsu Ltd 半導体装置及びその製造方法
KR20210013790A (ko) 2019-07-29 2021-02-08 삼성전자주식회사 반도체 메모리 장치

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US4771017A (en) * 1987-06-23 1988-09-13 Spire Corporation Patterning process
JPH01140652A (ja) * 1987-11-26 1989-06-01 Sharp Corp 立体型半導体装置
JPH0714028B2 (ja) * 1987-11-27 1995-02-15 シャープ株式会社 立体型半導体装置の製造方法
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Also Published As

Publication number Publication date
AU2001229896A1 (en) 2001-08-07
JP2003521125A (ja) 2003-07-08
DE60129793T2 (de) 2008-04-30
US20040029329A1 (en) 2004-02-12
EP1252654B1 (de) 2007-08-08
EP1252654A2 (de) 2002-10-30
US6812078B2 (en) 2004-11-02
WO2001056079A2 (en) 2001-08-02
US20030040145A1 (en) 2003-02-27
WO2001056079A3 (en) 2002-04-04
JP5022549B2 (ja) 2012-09-12
US6576505B2 (en) 2003-06-10

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Legal Events

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8364 No opposition during term of opposition