DE60134830D1 - System und verfahren zur kompensation von durch versorgungsspannung induzierten signalverzögerungsfehlanpassungen - Google Patents

System und verfahren zur kompensation von durch versorgungsspannung induzierten signalverzögerungsfehlanpassungen

Info

Publication number
DE60134830D1
DE60134830D1 DE60134830T DE60134830T DE60134830D1 DE 60134830 D1 DE60134830 D1 DE 60134830D1 DE 60134830 T DE60134830 T DE 60134830T DE 60134830 T DE60134830 T DE 60134830T DE 60134830 D1 DE60134830 D1 DE 60134830D1
Authority
DE
Germany
Prior art keywords
delay
adjustable
buffer
supply voltage
compensating signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60134830T
Other languages
English (en)
Inventor
Christian A Lutkemeyer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of DE60134830D1 publication Critical patent/DE60134830D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/002—Specific input/output arrangements not covered by G06F3/01 - G06F3/16
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
DE60134830T 2000-01-24 2001-01-24 System und verfahren zur kompensation von durch versorgungsspannung induzierten signalverzögerungsfehlanpassungen Expired - Lifetime DE60134830D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17777600P 2000-01-24 2000-01-24
US18242100P 2000-02-14 2000-02-14
PCT/US2001/002642 WO2001053916A2 (en) 2000-01-24 2001-01-24 System and method for compensating for supply voltage induced signal delay mismatches

Publications (1)

Publication Number Publication Date
DE60134830D1 true DE60134830D1 (de) 2008-08-28

Family

ID=26873631

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60134830T Expired - Lifetime DE60134830D1 (de) 2000-01-24 2001-01-24 System und verfahren zur kompensation von durch versorgungsspannung induzierten signalverzögerungsfehlanpassungen

Country Status (6)

Country Link
US (6) US6501311B2 (de)
EP (1) EP1250638B1 (de)
AT (1) ATE401597T1 (de)
AU (1) AU2001233023A1 (de)
DE (1) DE60134830D1 (de)
WO (1) WO2001053916A2 (de)

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US7571406B2 (en) * 2005-08-04 2009-08-04 Freescale Semiconductor, Inc. Clock tree adjustable buffer
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US7627839B1 (en) * 2005-11-14 2009-12-01 National Semiconductor Corporation Process corner indicator and estimation circuit
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US7486130B2 (en) * 2005-12-14 2009-02-03 Ember Corporation Clock skew compensation
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KR101370118B1 (ko) * 2007-09-28 2014-03-04 에이저 시스템즈 엘엘시 확장된 트래킹 범위를 갖는 위상 동기 루프(ｐｌｌ)
US8032778B2 (en) * 2008-03-19 2011-10-04 Micron Technology, Inc. Clock distribution apparatus, systems, and methods
JP5384910B2 (ja) 2008-11-11 2014-01-08 ルネサスエレクトロニクス株式会社 半導体集積回路及びクロック同期化制御方法
US7969219B2 (en) * 2008-11-26 2011-06-28 Texas Instruments Incorporated Wide range delay cell
US9143129B2 (en) * 2009-09-17 2015-09-22 Broadcom Corporation Low power, accurate reference-free threshold detector
JP5657902B2 (ja) * 2010-03-17 2015-01-21 株式会社コスモステクニカルセンター ポリオキシアルキレンステロールエーテル誘導体及び／又はポリオキシアルキレンスタノールエーテル誘導体、及びそれを含有する外用剤組成物
WO2014172252A1 (en) * 2013-04-15 2014-10-23 Kent State University Patterned liquid crystal alignment using ink-jet printed nanoparticles and use thereof to produce patterned, electro-optically addressable devices; ink-jet printable compositions
US9419589B2 (en) * 2013-08-16 2016-08-16 Apple Inc. Power source for clock distribution network
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US10419005B2 (en) * 2016-12-14 2019-09-17 Taiwan Semiconductor Manufacturing Co., Ltd. Phase-locked-loop architecture
KR20210073299A (ko) * 2019-12-10 2021-06-18 삼성전자주식회사 클록 데이터 복원 회로 및 이를 포함하는 장치
KR20220098854A (ko) 2021-01-05 2022-07-12 에스케이하이닉스 주식회사 지연 변동을 보상하는 반도체 장치 및 이를 포함하는 클록 전달 회로
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Also Published As

Publication number Publication date
US6501311B2 (en) 2002-12-31
WO2001053916A3 (en) 2002-05-02
US20040145397A1 (en) 2004-07-29
US6636091B2 (en) 2003-10-21
US6879196B2 (en) 2005-04-12
US20040025075A1 (en) 2004-02-05
WO2001053916A2 (en) 2001-07-26
EP1250638A2 (de) 2002-10-23
EP1250638B1 (de) 2008-07-16
US6693475B2 (en) 2004-02-17
US7049868B2 (en) 2006-05-23
WO2001053916A8 (en) 2001-10-04
AU2001233023A1 (en) 2001-07-31
US20020093367A1 (en) 2002-07-18
ATE401597T1 (de) 2008-08-15
US20030038663A1 (en) 2003-02-27
US6690216B2 (en) 2004-02-10
US20010049812A1 (en) 2001-12-06
US20020089362A1 (en) 2002-07-11

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Legal Events

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8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: BOSCH JEHLE PATENTANWALTSGESELLSCHAFT MBH, 80639 M