DE60140859D1 - Multiprozessorsystem mit gemeinsamem Speicher, welches gemischte Broadcast-Snoop und verzeichnisbasierte Kohärenzprotokolle benutzt - Google Patents

Multiprozessorsystem mit gemeinsamem Speicher, welches gemischte Broadcast-Snoop und verzeichnisbasierte Kohärenzprotokolle benutzt

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Publication number
DE60140859D1
DE60140859D1 DE60140859T DE60140859T DE60140859D1 DE 60140859 D1 DE60140859 D1 DE 60140859D1 DE 60140859 T DE60140859 T DE 60140859T DE 60140859 T DE60140859 T DE 60140859T DE 60140859 D1 DE60140859 D1 DE 60140859D1
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DE
Germany
Prior art keywords
mode
point
network
address
broadcast
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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DE60140859T
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English (en)
Inventor
Robert Cypher
Ashok Singhal
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Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
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Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE60140859D1 publication Critical patent/DE60140859D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • G06F12/0831Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • G06F12/0817Cache consistency protocols using directory methods
DE60140859T 2001-05-01 2001-05-01 Multiprozessorsystem mit gemeinsamem Speicher, welches gemischte Broadcast-Snoop und verzeichnisbasierte Kohärenzprotokolle benutzt Expired - Lifetime DE60140859D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP01303988A EP1255201B1 (de) 2001-05-01 2001-05-01 Multiprozessorsystem mit gemeinsamem Speicher, welches gemischte Broadcast-Snoop und verzeichnisbasierte Kohärenzprotokolle benutzt

Publications (1)

Publication Number Publication Date
DE60140859D1 true DE60140859D1 (de) 2010-02-04

Family

ID=8181936

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60140859T Expired - Lifetime DE60140859D1 (de) 2001-05-01 2001-05-01 Multiprozessorsystem mit gemeinsamem Speicher, welches gemischte Broadcast-Snoop und verzeichnisbasierte Kohärenzprotokolle benutzt

Country Status (4)

Country Link
US (1) US7032078B2 (de)
EP (1) EP1255201B1 (de)
AT (1) ATE453152T1 (de)
DE (1) DE60140859D1 (de)

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US7818391B2 (en) * 2004-01-20 2010-10-19 Hewlett-Packard Development Company, L.P. System and method to facilitate ordering point migration
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US8176259B2 (en) * 2004-01-20 2012-05-08 Hewlett-Packard Development Company, L.P. System and method for resolving transactions in a cache coherency protocol
US7143245B2 (en) * 2004-01-20 2006-11-28 Hewlett-Packard Development Company, L.P. System and method for read migratory optimization in a cache coherency protocol
US8145847B2 (en) * 2004-01-20 2012-03-27 Hewlett-Packard Development Company, L.P. Cache coherency protocol with ordering points
US8090914B2 (en) * 2004-01-20 2012-01-03 Hewlett-Packard Development Company, L.P. System and method for creating ordering points
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US8468308B2 (en) * 2004-01-20 2013-06-18 Hewlett-Packard Development Company, L.P. System and method for non-migratory requests in a cache coherency protocol
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US7177987B2 (en) * 2004-01-20 2007-02-13 Hewlett-Packard Development Company, L.P. System and method for responses between different cache coherency protocols
US7620696B2 (en) * 2004-01-20 2009-11-17 Hewlett-Packard Development Company, L.P. System and method for conflict responses in a cache coherency protocol
EP1782244A4 (de) * 2004-07-07 2010-01-20 Emc Corp Systeme und verfahren zur bereitstellung von kohärenz eines verteilten cache
US7467256B2 (en) * 2004-12-28 2008-12-16 Intel Corporation Processor having content addressable memory for block-based queue structures
US7480770B2 (en) * 2006-06-14 2009-01-20 Sun Microsystems, Inc. Semi-blocking deterministic directory coherence
RU2450328C1 (ru) * 2010-12-15 2012-05-10 Государственное образовательное учреждение высшего профессионального образования "Юго-Западный государственный университет" (ЮЗГУ) Логический мультиконтроллер с распределенным параллельно-конвейерным барьерным синхронизатором
US20160184571A1 (en) * 2013-09-09 2016-06-30 Nanopass Technologies Ltd. Prefilled Syringe Devices Employing Microneedle Interfaces for Intradermal Delivery
US9329890B2 (en) 2013-09-26 2016-05-03 Globalfoundries Inc. Managing high-coherence-miss cache lines in multi-processor computing environments
US9292444B2 (en) 2013-09-26 2016-03-22 International Business Machines Corporation Multi-granular cache management in multi-processor computing environments
US9086974B2 (en) * 2013-09-26 2015-07-21 International Business Machines Corporation Centralized management of high-contention cache lines in multi-processor computing environments
US9298623B2 (en) 2013-09-26 2016-03-29 Globalfoundries Inc. Identifying high-conflict cache lines in transactional memory computing environments
US9298626B2 (en) 2013-09-26 2016-03-29 Globalfoundries Inc. Managing high-conflict cache lines in transactional memory computing environments
KR102069696B1 (ko) * 2013-11-20 2020-01-23 한국전자통신연구원 캐시 제어 장치 및 방법
US10255183B2 (en) 2015-07-23 2019-04-09 Arteris, Inc. Victim buffer for cache coherent systems
US9542316B1 (en) * 2015-07-23 2017-01-10 Arteris, Inc. System and method for adaptation of coherence models between agents
US11656992B2 (en) * 2019-05-03 2023-05-23 Western Digital Technologies, Inc. Distributed cache with in-network prefetch
US11765250B2 (en) 2020-06-26 2023-09-19 Western Digital Technologies, Inc. Devices and methods for managing network traffic for a distributed cache
US11675706B2 (en) 2020-06-30 2023-06-13 Western Digital Technologies, Inc. Devices and methods for failure detection and recovery for a distributed cache
US11736417B2 (en) 2020-08-17 2023-08-22 Western Digital Technologies, Inc. Devices and methods for network message sequencing

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Also Published As

Publication number Publication date
US7032078B2 (en) 2006-04-18
ATE453152T1 (de) 2010-01-15
US20030018739A1 (en) 2003-01-23
EP1255201A1 (de) 2002-11-06
EP1255201B1 (de) 2009-12-23

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