DE60140859D1 - Multiprozessorsystem mit gemeinsamem Speicher, welches gemischte Broadcast-Snoop und verzeichnisbasierte Kohärenzprotokolle benutzt - Google Patents
Multiprozessorsystem mit gemeinsamem Speicher, welches gemischte Broadcast-Snoop und verzeichnisbasierte Kohärenzprotokolle benutztInfo
- Publication number
- DE60140859D1 DE60140859D1 DE60140859T DE60140859T DE60140859D1 DE 60140859 D1 DE60140859 D1 DE 60140859D1 DE 60140859 T DE60140859 T DE 60140859T DE 60140859 T DE60140859 T DE 60140859T DE 60140859 D1 DE60140859 D1 DE 60140859D1
- Authority
- DE
- Germany
- Prior art keywords
- mode
- point
- network
- address
- broadcast
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005540 biological transmission Effects 0.000 abstract 4
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP01303988A EP1255201B1 (de) | 2001-05-01 | 2001-05-01 | Multiprozessorsystem mit gemeinsamem Speicher, welches gemischte Broadcast-Snoop und verzeichnisbasierte Kohärenzprotokolle benutzt |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60140859D1 true DE60140859D1 (de) | 2010-02-04 |
Family
ID=8181936
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60140859T Expired - Lifetime DE60140859D1 (de) | 2001-05-01 | 2001-05-01 | Multiprozessorsystem mit gemeinsamem Speicher, welches gemischte Broadcast-Snoop und verzeichnisbasierte Kohärenzprotokolle benutzt |
Country Status (4)
Country | Link |
---|---|
US (1) | US7032078B2 (de) |
EP (1) | EP1255201B1 (de) |
AT (1) | ATE453152T1 (de) |
DE (1) | DE60140859D1 (de) |
Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8185602B2 (en) | 2002-11-05 | 2012-05-22 | Newisys, Inc. | Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters |
US8024526B2 (en) | 2003-04-11 | 2011-09-20 | Oracle America, Inc. | Multi-node system with global access states |
GB2416416B (en) * | 2003-04-11 | 2006-11-22 | Sun Microsystems Inc | Multi-node computer system implementing global access state dependent transactions |
US7529893B2 (en) * | 2003-04-11 | 2009-05-05 | Sun Microsystems, Inc. | Multi-node system with split ownership and access right coherence mechanism |
US7469321B2 (en) * | 2003-06-25 | 2008-12-23 | International Business Machines Corporation | Software process migration between coherency regions without cache purges |
US7484043B2 (en) * | 2003-06-25 | 2009-01-27 | International Business Machines Corporation | Multiprocessor system with dynamic cache coherency regions |
US7962696B2 (en) | 2004-01-15 | 2011-06-14 | Hewlett-Packard Development Company, L.P. | System and method for updating owner predictors |
US7240165B2 (en) * | 2004-01-15 | 2007-07-03 | Hewlett-Packard Development Company, L.P. | System and method for providing parallel data requests |
US7856534B2 (en) | 2004-01-15 | 2010-12-21 | Hewlett-Packard Development Company, L.P. | Transaction references for requests in a multi-processor network |
US7818391B2 (en) * | 2004-01-20 | 2010-10-19 | Hewlett-Packard Development Company, L.P. | System and method to facilitate ordering point migration |
US7149852B2 (en) * | 2004-01-20 | 2006-12-12 | Hewlett Packard Development Company, Lp. | System and method for blocking data responses |
US7395374B2 (en) | 2004-01-20 | 2008-07-01 | Hewlett-Packard Company, L.P. | System and method for conflict responses in a cache coherency protocol with ordering point migration |
US8176259B2 (en) * | 2004-01-20 | 2012-05-08 | Hewlett-Packard Development Company, L.P. | System and method for resolving transactions in a cache coherency protocol |
US7143245B2 (en) * | 2004-01-20 | 2006-11-28 | Hewlett-Packard Development Company, L.P. | System and method for read migratory optimization in a cache coherency protocol |
US8145847B2 (en) * | 2004-01-20 | 2012-03-27 | Hewlett-Packard Development Company, L.P. | Cache coherency protocol with ordering points |
US8090914B2 (en) * | 2004-01-20 | 2012-01-03 | Hewlett-Packard Development Company, L.P. | System and method for creating ordering points |
US20050160238A1 (en) * | 2004-01-20 | 2005-07-21 | Steely Simon C.Jr. | System and method for conflict responses in a cache coherency protocol with ordering point migration |
US8468308B2 (en) * | 2004-01-20 | 2013-06-18 | Hewlett-Packard Development Company, L.P. | System and method for non-migratory requests in a cache coherency protocol |
US7769959B2 (en) * | 2004-01-20 | 2010-08-03 | Hewlett-Packard Development Company, L.P. | System and method to facilitate ordering point migration to memory |
US7177987B2 (en) * | 2004-01-20 | 2007-02-13 | Hewlett-Packard Development Company, L.P. | System and method for responses between different cache coherency protocols |
US7620696B2 (en) * | 2004-01-20 | 2009-11-17 | Hewlett-Packard Development Company, L.P. | System and method for conflict responses in a cache coherency protocol |
EP1782244A4 (de) * | 2004-07-07 | 2010-01-20 | Emc Corp | Systeme und verfahren zur bereitstellung von kohärenz eines verteilten cache |
US7467256B2 (en) * | 2004-12-28 | 2008-12-16 | Intel Corporation | Processor having content addressable memory for block-based queue structures |
US7480770B2 (en) * | 2006-06-14 | 2009-01-20 | Sun Microsystems, Inc. | Semi-blocking deterministic directory coherence |
RU2450328C1 (ru) * | 2010-12-15 | 2012-05-10 | Государственное образовательное учреждение высшего профессионального образования "Юго-Западный государственный университет" (ЮЗГУ) | Логический мультиконтроллер с распределенным параллельно-конвейерным барьерным синхронизатором |
US20160184571A1 (en) * | 2013-09-09 | 2016-06-30 | Nanopass Technologies Ltd. | Prefilled Syringe Devices Employing Microneedle Interfaces for Intradermal Delivery |
US9329890B2 (en) | 2013-09-26 | 2016-05-03 | Globalfoundries Inc. | Managing high-coherence-miss cache lines in multi-processor computing environments |
US9292444B2 (en) | 2013-09-26 | 2016-03-22 | International Business Machines Corporation | Multi-granular cache management in multi-processor computing environments |
US9086974B2 (en) * | 2013-09-26 | 2015-07-21 | International Business Machines Corporation | Centralized management of high-contention cache lines in multi-processor computing environments |
US9298623B2 (en) | 2013-09-26 | 2016-03-29 | Globalfoundries Inc. | Identifying high-conflict cache lines in transactional memory computing environments |
US9298626B2 (en) | 2013-09-26 | 2016-03-29 | Globalfoundries Inc. | Managing high-conflict cache lines in transactional memory computing environments |
KR102069696B1 (ko) * | 2013-11-20 | 2020-01-23 | 한국전자통신연구원 | 캐시 제어 장치 및 방법 |
US10255183B2 (en) | 2015-07-23 | 2019-04-09 | Arteris, Inc. | Victim buffer for cache coherent systems |
US9542316B1 (en) * | 2015-07-23 | 2017-01-10 | Arteris, Inc. | System and method for adaptation of coherence models between agents |
US11656992B2 (en) * | 2019-05-03 | 2023-05-23 | Western Digital Technologies, Inc. | Distributed cache with in-network prefetch |
US11765250B2 (en) | 2020-06-26 | 2023-09-19 | Western Digital Technologies, Inc. | Devices and methods for managing network traffic for a distributed cache |
US11675706B2 (en) | 2020-06-30 | 2023-06-13 | Western Digital Technologies, Inc. | Devices and methods for failure detection and recovery for a distributed cache |
US11736417B2 (en) | 2020-08-17 | 2023-08-22 | Western Digital Technologies, Inc. | Devices and methods for network message sequencing |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04291446A (ja) * | 1990-12-05 | 1992-10-15 | Ncr Corp | スケーラブルメモリ帯域を備えた緊密結合型多重プロセッサ |
US6088768A (en) * | 1993-12-28 | 2000-07-11 | International Business Machines Corporation | Method and system for maintaining cache coherence in a multiprocessor-multicache environment having unordered communication |
US5887138A (en) * | 1996-07-01 | 1999-03-23 | Sun Microsystems, Inc. | Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes |
US5864671A (en) * | 1996-07-01 | 1999-01-26 | Sun Microsystems, Inc. | Hybrid memory access protocol for servicing memory access request by ascertaining whether the memory block is currently cached in determining which protocols to be used |
US5829034A (en) * | 1996-07-01 | 1998-10-27 | Sun Microsystems, Inc. | Method and apparatus for a coherence transformer with limited memory for connecting computer system coherence domains |
US5802582A (en) * | 1996-09-10 | 1998-09-01 | International Business Machines Corporation | Explicit coherence using split-phase controls |
US5966729A (en) * | 1997-06-30 | 1999-10-12 | Sun Microsystems, Inc. | Snoop filter for use in multiprocessor computer systems |
US6209064B1 (en) * | 1998-01-07 | 2001-03-27 | Fujitsu Limited | Cache coherence unit with integrated message passing and memory protection for a distributed, shared memory multiprocessor system |
US6751698B1 (en) * | 1999-09-29 | 2004-06-15 | Silicon Graphics, Inc. | Multiprocessor node controller circuit and method |
US6810467B1 (en) * | 2000-08-21 | 2004-10-26 | Intel Corporation | Method and apparatus for centralized snoop filtering |
US6883070B2 (en) * | 2001-03-14 | 2005-04-19 | Wisconsin Alumni Research Foundation | Bandwidth-adaptive, hybrid, cache-coherence protocol |
US7093079B2 (en) * | 2002-12-17 | 2006-08-15 | Intel Corporation | Snoop filter bypass |
-
2001
- 2001-05-01 EP EP01303988A patent/EP1255201B1/de not_active Expired - Lifetime
- 2001-05-01 DE DE60140859T patent/DE60140859D1/de not_active Expired - Lifetime
- 2001-05-01 AT AT01303988T patent/ATE453152T1/de not_active IP Right Cessation
-
2002
- 2002-05-01 US US10/136,619 patent/US7032078B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US7032078B2 (en) | 2006-04-18 |
ATE453152T1 (de) | 2010-01-15 |
US20030018739A1 (en) | 2003-01-23 |
EP1255201A1 (de) | 2002-11-06 |
EP1255201B1 (de) | 2009-12-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |