DE60141843D1 - Verfahren zur bildung einer schicht aus relaxiertem sige-auf-isolator - Google Patents

Verfahren zur bildung einer schicht aus relaxiertem sige-auf-isolator

Info

Publication number
DE60141843D1
DE60141843D1 DE60141843T DE60141843T DE60141843D1 DE 60141843 D1 DE60141843 D1 DE 60141843D1 DE 60141843 T DE60141843 T DE 60141843T DE 60141843 T DE60141843 T DE 60141843T DE 60141843 D1 DE60141843 D1 DE 60141843D1
Authority
DE
Germany
Prior art keywords
strained
ygey
layer
hydrogen
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60141843T
Other languages
English (en)
Inventor
Donald Canaperi
Jack Oon Chu
Emic Christopher D
Lijuan Huang
John Albert Ott
Hon-Sum Philip Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE60141843D1 publication Critical patent/DE60141843D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
DE60141843T 2000-09-29 2001-09-27 Verfahren zur bildung einer schicht aus relaxiertem sige-auf-isolator Expired - Lifetime DE60141843D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/675,840 US6524935B1 (en) 2000-09-29 2000-09-29 Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique
PCT/GB2001/004321 WO2002027783A1 (en) 2000-09-29 2001-09-27 PREPARATION OF A RELAXED SiGe LAYER ON AN INSULATOR

Publications (1)

Publication Number Publication Date
DE60141843D1 true DE60141843D1 (de) 2010-05-27

Family

ID=24712163

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60141843T Expired - Lifetime DE60141843D1 (de) 2000-09-29 2001-09-27 Verfahren zur bildung einer schicht aus relaxiertem sige-auf-isolator

Country Status (11)

Country Link
US (1) US6524935B1 (de)
EP (1) EP1320883B1 (de)
JP (1) JP4045187B2 (de)
KR (1) KR100532338B1 (de)
CN (1) CN1215550C (de)
AT (1) ATE464654T1 (de)
AU (1) AU2001292024A1 (de)
DE (1) DE60141843D1 (de)
MY (1) MY126089A (de)
TW (1) TW512487B (de)
WO (1) WO2002027783A1 (de)

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Also Published As

Publication number Publication date
JP4045187B2 (ja) 2008-02-13
EP1320883B1 (de) 2010-04-14
US6524935B1 (en) 2003-02-25
JP2004510350A (ja) 2004-04-02
CN1215550C (zh) 2005-08-17
WO2002027783A1 (en) 2002-04-04
TW512487B (en) 2002-12-01
KR100532338B1 (ko) 2005-11-29
AU2001292024A1 (en) 2002-04-08
ATE464654T1 (de) 2010-04-15
KR20030033078A (ko) 2003-04-26
CN1489786A (zh) 2004-04-14
EP1320883A1 (de) 2003-06-25
MY126089A (en) 2006-09-29

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