DE602004006516D1 - Parallel-verarbeitungs-array - Google Patents

Parallel-verarbeitungs-array

Info

Publication number
DE602004006516D1
DE602004006516D1 DE602004006516T DE602004006516T DE602004006516D1 DE 602004006516 D1 DE602004006516 D1 DE 602004006516D1 DE 602004006516 T DE602004006516 T DE 602004006516T DE 602004006516 T DE602004006516 T DE 602004006516T DE 602004006516 D1 DE602004006516 D1 DE 602004006516D1
Authority
DE
Germany
Prior art keywords
processing
parallel processing
processing array
alu
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004006516T
Other languages
English (en)
Other versions
DE602004006516T2 (de
Inventor
Om P Gangwal
Anteneh A Abbo
Richard P Kleihorst
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of DE602004006516D1 publication Critical patent/DE602004006516D1/de
Application granted granted Critical
Publication of DE602004006516T2 publication Critical patent/DE602004006516T2/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/22—Arrangements for sorting or merging computer data on continuous record carriers, e.g. tape, drum, disc
    • G06F7/32—Merging, i.e. combining data contained in ordered sequence on at least two record carriers to produce a single carrier or set of carriers having all the original data in the ordered sequence merging methods in general
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
DE602004006516T 2003-08-15 2004-08-03 Parallel-verarbeitungs-array Active DE602004006516T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP03102550 2003-08-15
EP03102550 2003-08-15
PCT/IB2004/051372 WO2005017765A2 (en) 2003-08-15 2004-08-03 Parallel processing array

Publications (2)

Publication Number Publication Date
DE602004006516D1 true DE602004006516D1 (de) 2007-06-28
DE602004006516T2 DE602004006516T2 (de) 2008-01-17

Family

ID=34178568

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004006516T Active DE602004006516T2 (de) 2003-08-15 2004-08-03 Parallel-verarbeitungs-array

Country Status (9)

Country Link
US (1) US7725681B2 (de)
EP (1) EP1656622B1 (de)
JP (1) JP2007503039A (de)
KR (1) KR20060060689A (de)
CN (1) CN100472505C (de)
AT (1) ATE362625T1 (de)
DE (1) DE602004006516T2 (de)
TW (1) TW200521702A (de)
WO (1) WO2005017765A2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7860915B2 (en) 2003-12-29 2010-12-28 Xilinx, Inc. Digital signal processing circuit having a pattern circuit for determining termination conditions
US7870182B2 (en) 2003-12-29 2011-01-11 Xilinx Inc. Digital signal processing circuit having an adder circuit with carry-outs
US7840630B2 (en) 2003-12-29 2010-11-23 Xilinx, Inc. Arithmetic logic unit circuit
US7865542B2 (en) 2003-12-29 2011-01-04 Xilinx, Inc. Digital signal processing block having a wide multiplexer
US7853634B2 (en) 2003-12-29 2010-12-14 Xilinx, Inc. Digital signal processing circuit having a SIMD circuit
US7840627B2 (en) * 2003-12-29 2010-11-23 Xilinx, Inc. Digital signal processing circuit having input register blocks
US7853632B2 (en) 2003-12-29 2010-12-14 Xilinx, Inc. Architectural floorplan for a digital signal processing circuit
US7844653B2 (en) 2003-12-29 2010-11-30 Xilinx, Inc. Digital signal processing circuit having a pre-adder circuit
US7882165B2 (en) 2003-12-29 2011-02-01 Xilinx, Inc. Digital signal processing element having an arithmetic logic unit
US7853636B2 (en) 2003-12-29 2010-12-14 Xilinx, Inc. Digital signal processing circuit having a pattern detector circuit for convergent rounding
US7849119B2 (en) 2003-12-29 2010-12-07 Xilinx, Inc. Digital signal processing circuit having a pattern detector circuit
WO2007029169A2 (en) * 2005-09-05 2007-03-15 Koninklijke Philips Electronics N.V. Processor array with separate serial module
US7441099B2 (en) * 2006-10-03 2008-10-21 Hong Kong Applied Science and Technology Research Institute Company Limited Configurable SIMD processor instruction specifying index to LUT storing information for different operation and memory location for each processing unit
US7958179B2 (en) 2006-12-06 2011-06-07 Electronics And Telecommunications Research Institute Arithmetic method and device of reconfigurable processor
CN101035071B (zh) * 2007-04-16 2010-09-29 中国人民解放军国防科学技术大学 并行simd结构中条件数据路由方法
EP2101258B1 (de) * 2008-03-10 2016-05-25 Mobileye Vision Technologies Ltd. Signalverarbeitung mit verbesserten Verweistabellen
US8543635B2 (en) 2009-01-27 2013-09-24 Xilinx, Inc. Digital signal processing block with preadder stage
US8479133B2 (en) 2009-01-27 2013-07-02 Xilinx, Inc. Method of and circuit for implementing a filter in an integrated circuit
CN102651797A (zh) * 2011-02-25 2012-08-29 西安邮电学院 一种新型阵列视频信号处理单元结构
CN103235762B (zh) * 2013-04-19 2016-06-22 中国科学院自动化研究所 一种自索引寄存器文件堆装置
US9830150B2 (en) * 2015-12-04 2017-11-28 Google Llc Multi-functional execution lane for image processor
US10586148B2 (en) * 2016-12-31 2020-03-10 Via Alliance Semiconductor Co., Ltd. Neural network unit with re-shapeable memory
US10565494B2 (en) * 2016-12-31 2020-02-18 Via Alliance Semiconductor Co., Ltd. Neural network unit with segmentable array width rotator
US10565492B2 (en) * 2016-12-31 2020-02-18 Via Alliance Semiconductor Co., Ltd. Neural network unit with segmentable array width rotator

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4025771A (en) * 1974-03-25 1977-05-24 Hughes Aircraft Company Pipe line high speed signal processor
JPH0743698B2 (ja) 1985-04-08 1995-05-15 工業技術院長 並列デ−タ処理装置
AU645785B2 (en) * 1990-01-05 1994-01-27 Maspar Computer Corporation Parallel processor memory system
US5717947A (en) * 1993-03-31 1998-02-10 Motorola, Inc. Data processing system and method thereof
US5526501A (en) * 1993-08-12 1996-06-11 Hughes Aircraft Company Variable accuracy indirect addressing scheme for SIMD multi-processors and apparatus implementing same
JPH0830577A (ja) 1994-07-15 1996-02-02 Mitsubishi Electric Corp Ｓｉｍｄプロセッサ
US5689677A (en) * 1995-06-05 1997-11-18 Macmillan; David C. Circuit for enhancing performance of a computer for personal use
US6272615B1 (en) * 1997-05-02 2001-08-07 Texas Instruments Incorporated Data processing device with an indexed immediate addressing mode
ATE362623T1 (de) * 1997-11-07 2007-06-15 Altera Corp Verfahren und gerät für effiziente, synchrone mimd-operationen mit ivliw pe-zu-pe kommunikationen
JP2001273267A (ja) * 2000-03-27 2001-10-05 Ricoh Co Ltd Ｓｉｍｄ型プロセッサー、並列処理装置、画像処理装置、複写機、プリンター、ファクシミリ装置、スキャナー、並列処理方法、画像処理方法およびその方法をコンピュータに実行させるプログラムを記録したコンピュータ読み取り可能な記録媒体
DE10159283A1 (de) * 2001-12-04 2003-06-12 Systemonic Ag Verfahren und Anordnung zur Adressgenerierung in einem Prozessor

Also Published As

Publication number Publication date
WO2005017765A2 (en) 2005-02-24
US20060253516A1 (en) 2006-11-09
ATE362625T1 (de) 2007-06-15
DE602004006516T2 (de) 2008-01-17
JP2007503039A (ja) 2007-02-15
CN100472505C (zh) 2009-03-25
WO2005017765A3 (en) 2005-04-21
TW200521702A (en) 2005-07-01
EP1656622A2 (de) 2006-05-17
KR20060060689A (ko) 2006-06-05
CN1836224A (zh) 2006-09-20
US7725681B2 (en) 2010-05-25
EP1656622B1 (de) 2007-05-16

Similar Documents

Publication Publication Date Title
ATE362625T1 (de) Parallel-verarbeitungs-array
WO2006130208A3 (en) Translation information retrieval
US20120191767A1 (en) Circuit which Performs Split Precision, Signed/Unsigned, Fixed and Floating Point, Real and Complex Multiplication
GB2436506A (en) Register file regions for a processing system
KR101482540B1 (ko) 중첩된 피연산자들을 갖는 ｓｉｍｄ 내적 연산들
CN101203830A (zh) 用于在交错的多线程环境中操作的数字信号处理器的寄存器堆
ATE371893T1 (de) Akkumulations-(mac-)einheit für einzelanweisungs- / mehrfachdaten-(simd-) anweisungen
GB2437684B (en) Data processor adapted for efficient digital signal processing and method therefor
DK2229631T3 (da) Dynamisk adresseomsætning med rammestyring
WO2006110906A3 (en) Unified non-partitioned register files for a digital signal processor operating in an interleaved multi-threaded environment
JP2007505373A5 (de)
TW200745850A (en) Lookup table addressing system and method
WO2006084289A3 (en) Fractional-word writable architected register for direct accumulation of misaligned data
GB0328542D0 (en) Data element size control within parallel lanes of processing
GB2419005B (en) Providing a register file memory with local addressing in a SIMD parallel processor
DE60115609D1 (de) Datenverarbeitungsarchitektur mit bereichsprüfung für matrix
KR102000894B1 (ko) 이미지 프로세서용 다기능 실행 레인
ATE456829T1 (de) Datenverarbeitungsschaltung mit funktionseinheiten mit gemeinsamen leseports
EP1089168A3 (de) Prozessor mit sehr langem Befehlswort
MY135903A (en) Result partitioning within simd data processing systems
ATE521033T1 (de) Dynamisch umkonfigurierbarer datenraum
MY158872A (en) Polynomial data processing operation
GB2382674B (en) Data access in a processor
US6320813B1 (en) Decoding of a register file
DE50210759D1 (de) Prozessor mit interner speicherkonfiguration und anordnung mit diesem prozessor

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL

8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

R082 Change of representative

Ref document number: 1656622

Country of ref document: EP

Representative=s name: MUELLER-BORE & PARTNER PATENTANWAELTE, EUROPEA, DE