DE602004007536D1 - Stromarme programmiertechnik für einen schwebkörper-speichertransistor, speicherzelle und speichermatrix - Google Patents
Stromarme programmiertechnik für einen schwebkörper-speichertransistor, speicherzelle und speichermatrixInfo
- Publication number
- DE602004007536D1 DE602004007536D1 DE602004007536T DE602004007536T DE602004007536D1 DE 602004007536 D1 DE602004007536 D1 DE 602004007536D1 DE 602004007536 T DE602004007536 T DE 602004007536T DE 602004007536 T DE602004007536 T DE 602004007536T DE 602004007536 D1 DE602004007536 D1 DE 602004007536D1
- Authority
- DE
- Germany
- Prior art keywords
- memory
- memory cell
- state
- floating body
- electrically floating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 abstract 2
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/4016—Memory devices with silicon-on-insulator cells
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US50567903P | 2003-09-24 | 2003-09-24 | |
| US505679P | 2003-09-24 | ||
| US10/941,692 US7184298B2 (en) | 2003-09-24 | 2004-09-15 | Low power programming technique for a floating body memory transistor, memory cell, and memory array |
| US941692 | 2004-09-15 | ||
| PCT/IB2004/003721 WO2005029499A2 (en) | 2003-09-24 | 2004-09-23 | Low power programming technique for a floating body memory transistor, memory cell, and memory array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE602004007536D1 true DE602004007536D1 (de) | 2007-08-23 |
| DE602004007536T2 DE602004007536T2 (de) | 2008-03-20 |
Family
ID=34316804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE602004007536T Active DE602004007536T2 (de) | 2003-09-24 | 2004-09-23 | Stromarme programmiertechnik für einen schwebkörper-speichertransistor, speicherzelle und speichermatrix |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US7184298B2 (de) |
| EP (1) | EP1671331B1 (de) |
| AT (1) | ATE366983T1 (de) |
| DE (1) | DE602004007536T2 (de) |
| WO (1) | WO2005029499A2 (de) |
Families Citing this family (82)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7002842B2 (en) * | 2003-11-26 | 2006-02-21 | Intel Corporation | Floating-body dynamic random access memory with purge line |
| US6903984B1 (en) * | 2003-12-31 | 2005-06-07 | Intel Corporation | Floating-body DRAM using write word line for increased retention time |
| US7547945B2 (en) * | 2004-09-01 | 2009-06-16 | Micron Technology, Inc. | Transistor devices, transistor structures and semiconductor constructions |
| US7301803B2 (en) * | 2004-12-22 | 2007-11-27 | Innovative Silicon S.A. | Bipolar reading technique for a memory cell having an electrically floating body transistor |
| US7384849B2 (en) * | 2005-03-25 | 2008-06-10 | Micron Technology, Inc. | Methods of forming recessed access devices associated with semiconductor constructions |
| JP4684719B2 (ja) * | 2005-04-07 | 2011-05-18 | パナソニック株式会社 | 半導体記憶装置 |
| US7538389B2 (en) * | 2005-06-08 | 2009-05-26 | Micron Technology, Inc. | Capacitorless DRAM on bulk silicon |
| US7282401B2 (en) | 2005-07-08 | 2007-10-16 | Micron Technology, Inc. | Method and apparatus for a self-aligned recessed access device (RAD) transistor gate |
| US20070023833A1 (en) * | 2005-07-28 | 2007-02-01 | Serguei Okhonin | Method for reading a memory cell having an electrically floating body transistor, and memory cell and array implementing same |
| US7867851B2 (en) * | 2005-08-30 | 2011-01-11 | Micron Technology, Inc. | Methods of forming field effect transistors on substrates |
| US7606066B2 (en) * | 2005-09-07 | 2009-10-20 | Innovative Silicon Isi Sa | Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same |
| US7355916B2 (en) * | 2005-09-19 | 2008-04-08 | Innovative Silicon S.A. | Method and circuitry to generate a reference current for reading a memory cell, and device implementing same |
| DE102006058865B4 (de) * | 2005-12-07 | 2010-06-10 | Samsung Electronics Co., Ltd., Suwon | Halbleiterspeicherbauelement und Verfahren zum Schreiben von Daten |
| KR100663368B1 (ko) * | 2005-12-07 | 2007-01-02 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 데이터 라이트 및 리드방법 |
| DE102007001783B4 (de) | 2006-01-06 | 2018-03-29 | Samsung Electronics Co., Ltd. | Halbleiter-Speicherelement, Verfahren zum Schreiben oder Wiederherstellen einer Schwellspannung und zum Betreiben eines Halbleiter-Speicherelements |
| KR100675300B1 (ko) * | 2006-01-06 | 2007-01-29 | 삼성전자주식회사 | 캐패시터가 없는 동적 메모리 셀을 구비한 반도체 메모리장치 및 이 장치의 데이터 라이트 및 리드 방법 |
| US7700441B2 (en) | 2006-02-02 | 2010-04-20 | Micron Technology, Inc. | Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates |
| US7542345B2 (en) * | 2006-02-16 | 2009-06-02 | Innovative Silicon Isi Sa | Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same |
| US7492632B2 (en) * | 2006-04-07 | 2009-02-17 | Innovative Silicon Isi Sa | Memory array having a programmable word length, and method of operating same |
| WO2007128738A1 (en) * | 2006-05-02 | 2007-11-15 | Innovative Silicon Sa | Semiconductor memory cell and array using punch-through to program and read same |
| US7499352B2 (en) * | 2006-05-19 | 2009-03-03 | Innovative Silicon Isi Sa | Integrated circuit having memory array including row redundancy, and method of programming, controlling and/or operating same |
| TWI302311B (en) * | 2006-06-09 | 2008-10-21 | Innolux Display Corp | Dynamic random access memory |
| US8069377B2 (en) | 2006-06-26 | 2011-11-29 | Micron Technology, Inc. | Integrated circuit having memory array including ECC and column redundancy and method of operating the same |
| US7542340B2 (en) * | 2006-07-11 | 2009-06-02 | Innovative Silicon Isi Sa | Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same |
| US7602001B2 (en) | 2006-07-17 | 2009-10-13 | Micron Technology, Inc. | Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells |
| US7733707B2 (en) * | 2006-07-21 | 2010-06-08 | Hynix Semiconductor Inc. | 1-transistor type DRAM cell, DRAM device and DRAM comprising thereof and driving method thereof and manufacturing method thereof |
| US7772632B2 (en) * | 2006-08-21 | 2010-08-10 | Micron Technology, Inc. | Memory arrays and methods of fabricating memory arrays |
| US7589995B2 (en) * | 2006-09-07 | 2009-09-15 | Micron Technology, Inc. | One-transistor memory cell with bias gate |
| US7410856B2 (en) * | 2006-09-14 | 2008-08-12 | Micron Technology, Inc. | Methods of forming vertical transistors |
| US7675771B2 (en) * | 2006-11-24 | 2010-03-09 | Samsung Electronics Co., Ltd. | Capacitor-less DRAM circuit and method of operating the same |
| KR20080058798A (ko) * | 2006-12-22 | 2008-06-26 | 삼성전자주식회사 | 커패시터리스 동적 반도체 메모리 장치 및 이 장치의 동작방법 |
| US8264041B2 (en) * | 2007-01-26 | 2012-09-11 | Micron Technology, Inc. | Semiconductor device with electrically floating body |
| RU2330011C1 (ru) * | 2007-03-01 | 2008-07-27 | Общество с ограниченной ответственностью "Еврохим-СПб-Трейдинг" | Способ получения фенола и ацетона |
| WO2009031052A2 (en) | 2007-03-29 | 2009-03-12 | Innovative Silicon S.A. | Zero-capacitor (floating body) random access memory circuits with polycide word lines and manufacturing methods therefor |
| US8064274B2 (en) * | 2007-05-30 | 2011-11-22 | Micron Technology, Inc. | Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same |
| US8085594B2 (en) * | 2007-06-01 | 2011-12-27 | Micron Technology, Inc. | Reading technique for memory cell with electrically floating body transistor |
| US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
| US7652910B2 (en) | 2007-06-30 | 2010-01-26 | Intel Corporation | Floating body memory array |
| US7630262B2 (en) * | 2007-07-04 | 2009-12-08 | Hynix Semiconductor, Inc. | One-transistor type dram |
| WO2009039169A1 (en) | 2007-09-17 | 2009-03-26 | Innovative Silicon S.A. | Refreshing data of memory cells with electrically floating body transistors |
| US20090078999A1 (en) * | 2007-09-20 | 2009-03-26 | Anderson Brent A | Semiconductor device structures with floating body charge storage and methods for forming such semiconductor device structures. |
| CN101889340A (zh) * | 2007-10-01 | 2010-11-17 | 佛罗里达大学研究基金公司 | 双晶体管浮体动态存储单元 |
| US8787072B2 (en) * | 2007-10-01 | 2014-07-22 | University Of Florida Research Foundation, Inc. | Floating-body/gate DRAM cell |
| US7948008B2 (en) * | 2007-10-26 | 2011-05-24 | Micron Technology, Inc. | Floating body field-effect transistors, and methods of forming floating body field-effect transistors |
| US8536628B2 (en) | 2007-11-29 | 2013-09-17 | Micron Technology, Inc. | Integrated circuit having memory cell array including barriers, and method of manufacturing same |
| US8349662B2 (en) * | 2007-12-11 | 2013-01-08 | Micron Technology, Inc. | Integrated circuit having memory cell array, and method of manufacturing same |
| KR101003115B1 (ko) * | 2007-12-12 | 2010-12-21 | 주식회사 하이닉스반도체 | 플로팅 바디 캐패시터를 구비한 반도체 메모리 소자 및 그제조방법 |
| US8773933B2 (en) | 2012-03-16 | 2014-07-08 | Micron Technology, Inc. | Techniques for accessing memory cells |
| US8014195B2 (en) * | 2008-02-06 | 2011-09-06 | Micron Technology, Inc. | Single transistor memory cell |
| US8189376B2 (en) * | 2008-02-08 | 2012-05-29 | Micron Technology, Inc. | Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same |
| US7957206B2 (en) * | 2008-04-04 | 2011-06-07 | Micron Technology, Inc. | Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same |
| KR101442175B1 (ko) * | 2008-05-23 | 2014-09-18 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 메모리 셀 어레이의 배치방법 |
| US7947543B2 (en) | 2008-09-25 | 2011-05-24 | Micron Technology, Inc. | Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation |
| US7933140B2 (en) | 2008-10-02 | 2011-04-26 | Micron Technology, Inc. | Techniques for reducing a voltage swing |
| US7924630B2 (en) * | 2008-10-15 | 2011-04-12 | Micron Technology, Inc. | Techniques for simultaneously driving a plurality of source lines |
| KR101497542B1 (ko) * | 2008-10-21 | 2015-03-02 | 삼성전자주식회사 | 반도체 소자의 동작 방법 |
| US8223574B2 (en) * | 2008-11-05 | 2012-07-17 | Micron Technology, Inc. | Techniques for block refreshing a semiconductor memory device |
| KR20100062215A (ko) * | 2008-12-01 | 2010-06-10 | 삼성전자주식회사 | 반도체 소자의 동작 방법 |
| US8213226B2 (en) * | 2008-12-05 | 2012-07-03 | Micron Technology, Inc. | Vertical transistor memory cell and array |
| US7977172B2 (en) * | 2008-12-08 | 2011-07-12 | Advanced Micro Devices, Inc. | Dynamic random access memory (DRAM) cells and methods for fabricating the same |
| US8319294B2 (en) * | 2009-02-18 | 2012-11-27 | Micron Technology, Inc. | Techniques for providing a source line plane |
| KR101585615B1 (ko) * | 2009-02-26 | 2016-01-14 | 삼성전자주식회사 | 반도체 장치 |
| US8710566B2 (en) | 2009-03-04 | 2014-04-29 | Micron Technology, Inc. | Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device |
| JP2010218629A (ja) * | 2009-03-17 | 2010-09-30 | Toshiba Corp | 半導体記憶装置 |
| KR20120006516A (ko) | 2009-03-31 | 2012-01-18 | 마이크론 테크놀로지, 인크. | 반도체 메모리 디바이스를 제공하기 위한 기술들 |
| US8139418B2 (en) | 2009-04-27 | 2012-03-20 | Micron Technology, Inc. | Techniques for controlling a direct injection semiconductor memory device |
| US8508994B2 (en) * | 2009-04-30 | 2013-08-13 | Micron Technology, Inc. | Semiconductor device with floating gate and electrically floating body |
| US8498157B2 (en) | 2009-05-22 | 2013-07-30 | Micron Technology, Inc. | Techniques for providing a direct injection semiconductor memory device |
| US8537610B2 (en) | 2009-07-10 | 2013-09-17 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device |
| US9076543B2 (en) * | 2009-07-27 | 2015-07-07 | Micron Technology, Inc. | Techniques for providing a direct injection semiconductor memory device |
| US8199595B2 (en) * | 2009-09-04 | 2012-06-12 | Micron Technology, Inc. | Techniques for sensing a semiconductor memory device |
| US8174881B2 (en) | 2009-11-24 | 2012-05-08 | Micron Technology, Inc. | Techniques for reducing disturbance in a semiconductor device |
| US8310893B2 (en) * | 2009-12-16 | 2012-11-13 | Micron Technology, Inc. | Techniques for reducing impact of array disturbs in a semiconductor memory device |
| US8416636B2 (en) | 2010-02-12 | 2013-04-09 | Micron Technology, Inc. | Techniques for controlling a semiconductor memory device |
| US8411513B2 (en) * | 2010-03-04 | 2013-04-02 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device having hierarchical bit lines |
| US8576631B2 (en) * | 2010-03-04 | 2013-11-05 | Micron Technology, Inc. | Techniques for sensing a semiconductor memory device |
| US8369177B2 (en) * | 2010-03-05 | 2013-02-05 | Micron Technology, Inc. | Techniques for reading from and/or writing to a semiconductor memory device |
| EP2548227B1 (de) | 2010-03-15 | 2021-07-14 | Micron Technology, Inc. | Verfahren zur bereitstellung einer halbleiterspeichervorrichtung |
| US8411524B2 (en) | 2010-05-06 | 2013-04-02 | Micron Technology, Inc. | Techniques for refreshing a semiconductor memory device |
| US8957458B2 (en) | 2011-03-24 | 2015-02-17 | Zeno Semiconductor, Inc. | Asymmetric semiconductor memory device having electrically floating body transistor |
| US8531878B2 (en) | 2011-05-17 | 2013-09-10 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device |
| US9559216B2 (en) | 2011-06-06 | 2017-01-31 | Micron Technology, Inc. | Semiconductor memory device and method for biasing same |
Family Cites Families (123)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3439214A (en) * | 1968-03-04 | 1969-04-15 | Fairchild Camera Instr Co | Beam-junction scan converter |
| US4032947A (en) * | 1971-10-20 | 1977-06-28 | Siemens Aktiengesellschaft | Controllable charge-coupled semiconductor device |
| US3997799A (en) | 1975-09-15 | 1976-12-14 | Baker Roger T | Semiconductor-device for the storage of binary data |
| JPS5567993A (en) * | 1978-11-14 | 1980-05-22 | Fujitsu Ltd | Semiconductor memory unit |
| US4250569A (en) * | 1978-11-15 | 1981-02-10 | Fujitsu Limited | Semiconductor memory device |
| DE3065928D1 (en) | 1979-01-25 | 1984-01-26 | Nec Corp | Semiconductor memory device |
| JPS55113359A (en) * | 1979-02-22 | 1980-09-01 | Fujitsu Ltd | Semiconductor integrated circuit device |
| JPS5742161A (en) * | 1980-08-28 | 1982-03-09 | Fujitsu Ltd | Semiconductor and production thereof |
| JPS6070760A (ja) | 1983-09-27 | 1985-04-22 | Fujitsu Ltd | 半導体記憶装置 |
| JPS61280651A (ja) | 1985-05-24 | 1986-12-11 | Fujitsu Ltd | 半導体記憶装置 |
| JP2582794B2 (ja) | 1987-08-10 | 1997-02-19 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US5144390A (en) | 1988-09-02 | 1992-09-01 | Texas Instruments Incorporated | Silicon-on insulator transistor with internal body node to source node connection |
| US5258635A (en) | 1988-09-06 | 1993-11-02 | Kabushiki Kaisha Toshiba | MOS-type semiconductor integrated circuit device |
| US5024993A (en) * | 1990-05-02 | 1991-06-18 | Microelectronics & Computer Technology Corporation | Superconducting-semiconducting circuits, devices and systems |
| US5420055A (en) * | 1992-01-22 | 1995-05-30 | Kopin Corporation | Reduction of parasitic effects in floating body MOSFETs |
| US5528062A (en) | 1992-06-17 | 1996-06-18 | International Business Machines Corporation | High-density DRAM structure on soi |
| EP0606758B1 (de) * | 1992-12-30 | 2000-09-06 | Samsung Electronics Co., Ltd. | Verfahren zur Herstellung einer SOI-Transistor-DRAM |
| US5448513A (en) | 1993-12-02 | 1995-09-05 | Regents Of The University Of California | Capacitorless DRAM device on silicon-on-insulator substrate |
| US5489792A (en) * | 1994-04-07 | 1996-02-06 | Regents Of The University Of California | Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility |
| US5446299A (en) * | 1994-04-29 | 1995-08-29 | International Business Machines Corporation | Semiconductor random access memory cell on silicon-on-insulator with dual control gates |
| US5627092A (en) * | 1994-09-26 | 1997-05-06 | Siemens Aktiengesellschaft | Deep trench dram process on SOI for low leakage DRAM cell |
| JP3304635B2 (ja) * | 1994-09-26 | 2002-07-22 | 三菱電機株式会社 | 半導体記憶装置 |
| US5593912A (en) * | 1994-10-06 | 1997-01-14 | International Business Machines Corporation | SOI trench DRAM cell for 256 MB DRAM and beyond |
| FR2726935B1 (fr) | 1994-11-10 | 1996-12-13 | Commissariat Energie Atomique | Dispositif a memoire non-volatile electriquement effacable et procede de realisation d'un tel dispositif |
| JP3274306B2 (ja) * | 1995-01-20 | 2002-04-15 | 株式会社東芝 | 半導体集積回路装置 |
| US6292424B1 (en) | 1995-01-20 | 2001-09-18 | Kabushiki Kaisha Toshiba | DRAM having a power supply voltage lowering circuit |
| JP2806286B2 (ja) * | 1995-02-07 | 1998-09-30 | 日本電気株式会社 | 半導体装置 |
| JP3600335B2 (ja) * | 1995-03-27 | 2004-12-15 | 株式会社東芝 | 半導体装置 |
| US5568356A (en) | 1995-04-18 | 1996-10-22 | Hughes Aircraft Company | Stacked module assembly including electrically interconnected switching module and plural electronic modules |
| US5606188A (en) * | 1995-04-26 | 1997-02-25 | International Business Machines Corporation | Fabrication process and structure for a contacted-body silicon-on-insulator dynamic random access memory |
| US5629546A (en) * | 1995-06-21 | 1997-05-13 | Micron Technology, Inc. | Static memory cell and method of manufacturing a static memory cell |
| US5585285A (en) | 1995-12-06 | 1996-12-17 | Micron Technology, Inc. | Method of forming dynamic random access memory circuitry using SOI and isolation trenches |
| JP3759648B2 (ja) * | 1996-03-04 | 2006-03-29 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| US5936265A (en) * | 1996-03-25 | 1999-08-10 | Kabushiki Kaisha Toshiba | Semiconductor device including a tunnel effect element |
| US6424016B1 (en) * | 1996-05-24 | 2002-07-23 | Texas Instruments Incorporated | SOI DRAM having P-doped polysilicon gate for a memory pass transistor |
| US5886376A (en) | 1996-07-01 | 1999-03-23 | International Business Machines Corporation | EEPROM having coplanar on-insulator FET and control gate |
| US5778243A (en) * | 1996-07-03 | 1998-07-07 | International Business Machines Corporation | Multi-threaded cell for a memory |
| US5811283A (en) | 1996-08-13 | 1998-09-22 | United Microelectronics Corporation | Silicon on insulator (SOI) dram cell structure and process |
| JP3260660B2 (ja) * | 1996-08-22 | 2002-02-25 | 株式会社東芝 | 半導体装置およびその製造方法 |
| JP2877103B2 (ja) * | 1996-10-21 | 1999-03-31 | 日本電気株式会社 | 不揮発性半導体記憶装置およびその製造方法 |
| KR19980057003A (ko) * | 1996-12-30 | 1998-09-25 | 김영환 | 반도체 메모리 디바이스 및 그 제조방법 |
| US5732014A (en) * | 1997-02-20 | 1998-03-24 | Micron Technology, Inc. | Merged transistor structure for gain memory cell |
| JP3441330B2 (ja) * | 1997-02-28 | 2003-09-02 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US6424011B1 (en) * | 1997-04-14 | 2002-07-23 | International Business Machines Corporation | Mixed memory integration with NVRAM, dram and sram cell structures on same substrate |
| US5784311A (en) * | 1997-06-13 | 1998-07-21 | International Business Machines Corporation | Two-device memory cell on SOI for merged logic and memory applications |
| US5943581A (en) * | 1997-11-05 | 1999-08-24 | Vanguard International Semiconductor Corporation | Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits |
| US5976945A (en) * | 1997-11-20 | 1999-11-02 | Vanguard International Semiconductor Corporation | Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor |
| US6020222A (en) * | 1997-12-16 | 2000-02-01 | Advanced Micro Devices, Inc. | Silicon oxide insulator (SOI) semiconductor having selectively linked body |
| US5943258A (en) * | 1997-12-24 | 1999-08-24 | Texas Instruments Incorporated | Memory with storage cells having SOI drive and access transistors with tied floating body connections |
| US6097056A (en) * | 1998-04-28 | 2000-08-01 | International Business Machines Corporation | Field effect transistor having a floating gate |
| US6225158B1 (en) * | 1998-05-28 | 2001-05-01 | International Business Machines Corporation | Trench storage dynamic random access memory cell with vertical transfer device |
| TW432545B (en) * | 1998-08-07 | 2001-05-01 | Ibm | Method and improved SOI body contact structure for transistors |
| KR100268419B1 (ko) | 1998-08-14 | 2000-10-16 | 윤종용 | 고집적 반도체 메모리 장치 및 그의 제조 방법 |
| US6096598A (en) * | 1998-10-29 | 2000-08-01 | International Business Machines Corporation | Method for forming pillar memory cells and device formed thereby |
| US6214694B1 (en) * | 1998-11-17 | 2001-04-10 | International Business Machines Corporation | Process of making densely patterned silicon-on-insulator (SOI) region on a wafer |
| KR100290787B1 (ko) | 1998-12-26 | 2001-07-12 | 박종섭 | 반도체 메모리 소자의 제조방법 |
| US6157216A (en) | 1999-04-22 | 2000-12-05 | International Business Machines Corporation | Circuit driver on SOI for merged logic and memory circuits |
| US6111778A (en) * | 1999-05-10 | 2000-08-29 | International Business Machines Corporation | Body contacted dynamic memory |
| US6213869B1 (en) | 1999-05-10 | 2001-04-10 | Advanced Micro Devices, Inc. | MOSFET-type device with higher driver current and lower steady state power dissipation |
| US6333532B1 (en) | 1999-07-16 | 2001-12-25 | International Business Machines Corporation | Patterned SOI regions in semiconductor chips |
| US6566177B1 (en) * | 1999-10-25 | 2003-05-20 | International Business Machines Corporation | Silicon-on-insulator vertical array device trench capacitor DRAM |
| US6391658B1 (en) * | 1999-10-26 | 2002-05-21 | International Business Machines Corporation | Formation of arrays of microelectronic elements |
| KR100350575B1 (ko) * | 1999-11-05 | 2002-08-28 | 주식회사 하이닉스반도체 | 소오스-바디-기판이 접촉된 이중막 실리콘 소자 및 제조방법 |
| US6544837B1 (en) * | 2000-03-17 | 2003-04-08 | International Business Machines Corporation | SOI stacked DRAM logic |
| US6359802B1 (en) * | 2000-03-28 | 2002-03-19 | Intel Corporation | One-transistor and one-capacitor DRAM cell for logic process technology |
| JP4011833B2 (ja) | 2000-06-30 | 2007-11-21 | 株式会社東芝 | 半導体メモリ |
| KR100339425B1 (ko) * | 2000-07-21 | 2002-06-03 | 박종섭 | 리세스된 소이 구조를 갖는 반도체 소자 및 그의 제조 방법 |
| US6621725B2 (en) * | 2000-08-17 | 2003-09-16 | Kabushiki Kaisha Toshiba | Semiconductor memory device with floating storage bulk region and method of manufacturing the same |
| US6492211B1 (en) | 2000-09-07 | 2002-12-10 | International Business Machines Corporation | Method for novel SOI DRAM BICMOS NPN |
| US20020070411A1 (en) * | 2000-09-08 | 2002-06-13 | Alcatel | Method of processing a high voltage p++/n-well junction and a device manufactured by the method |
| JP4064607B2 (ja) * | 2000-09-08 | 2008-03-19 | 株式会社東芝 | 半導体メモリ装置 |
| JP2002094027A (ja) * | 2000-09-11 | 2002-03-29 | Toshiba Corp | 半導体記憶装置とその製造方法 |
| US6350653B1 (en) * | 2000-10-12 | 2002-02-26 | International Business Machines Corporation | Embedded DRAM on silicon-on-insulator substrate |
| US6421269B1 (en) * | 2000-10-17 | 2002-07-16 | Intel Corporation | Low-leakage MOS planar capacitors for use within DRAM storage cells |
| US6496402B1 (en) * | 2000-10-17 | 2002-12-17 | Intel Corporation | Noise suppression for open bit line DRAM architectures |
| US6849871B2 (en) * | 2000-10-20 | 2005-02-01 | International Business Machines Corporation | Fully-depleted-collector silicon-on-insulator (SOI) bipolar transistor useful alone or in SOI BiCMOS |
| US6429477B1 (en) | 2000-10-31 | 2002-08-06 | International Business Machines Corporation | Shared body and diffusion contact structure and method for fabricating same |
| US6440872B1 (en) | 2000-11-03 | 2002-08-27 | International Business Machines Corporation | Method for hybrid DRAM cell utilizing confined strap isolation |
| US6549450B1 (en) * | 2000-11-08 | 2003-04-15 | Ibm Corporation | Method and system for improving the performance on SOI memory arrays in an SRAM architecture system |
| US6441436B1 (en) | 2000-11-29 | 2002-08-27 | United Microelectronics Corp. | SOI device and method of fabrication |
| JP3808700B2 (ja) * | 2000-12-06 | 2006-08-16 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US20020072155A1 (en) * | 2000-12-08 | 2002-06-13 | Chih-Cheng Liu | Method of fabricating a DRAM unit |
| US7101772B2 (en) * | 2000-12-30 | 2006-09-05 | Texas Instruments Incorporated | Means for forming SOI |
| US6552398B2 (en) * | 2001-01-16 | 2003-04-22 | Ibm Corporation | T-Ram array having a planar cell structure and method for fabricating the same |
| US6441435B1 (en) | 2001-01-31 | 2002-08-27 | Advanced Micro Devices, Inc. | SOI device with wrap-around contact to underside of body, and method of making |
| JP4216483B2 (ja) * | 2001-02-15 | 2009-01-28 | 株式会社東芝 | 半導体メモリ装置 |
| JP3884266B2 (ja) | 2001-02-19 | 2007-02-21 | 株式会社東芝 | 半導体メモリ装置及びその製造方法 |
| US6548848B2 (en) * | 2001-03-15 | 2003-04-15 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| JP4071476B2 (ja) * | 2001-03-21 | 2008-04-02 | 株式会社東芝 | 半導体ウェーハ及び半導体ウェーハの製造方法 |
| EP1253634A3 (de) | 2001-04-26 | 2005-08-31 | Kabushiki Kaisha Toshiba | Halbleiterbauelement |
| US6556477B2 (en) * | 2001-05-21 | 2003-04-29 | Ibm Corporation | Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same |
| TWI230392B (en) * | 2001-06-18 | 2005-04-01 | Innovative Silicon Sa | Semiconductor device |
| EP1271547A1 (de) * | 2001-06-18 | 2003-01-02 | Innovative Silicon SA | Halbleitervorrichtung und DRAM Speicher |
| US6756637B2 (en) * | 2001-07-06 | 2004-06-29 | International Business Machines Corporation | Method of controlling floating body effects in an asymmetrical SOI device |
| JP2003031693A (ja) * | 2001-07-19 | 2003-01-31 | Toshiba Corp | 半導体メモリ装置 |
| US6567330B2 (en) * | 2001-08-17 | 2003-05-20 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| JP3984014B2 (ja) * | 2001-09-26 | 2007-09-26 | 株式会社東芝 | 半導体装置用基板を製造する方法および半導体装置用基板 |
| JP4322453B2 (ja) * | 2001-09-27 | 2009-09-02 | 株式会社東芝 | 半導体装置およびその製造方法 |
| US6657259B2 (en) * | 2001-12-04 | 2003-12-02 | International Business Machines Corporation | Multiple-plane FinFET CMOS |
| US6518105B1 (en) * | 2001-12-10 | 2003-02-11 | Taiwan Semiconductor Manufacturing Company | High performance PD SOI tunneling-biased MOSFET |
| JP2003203967A (ja) * | 2001-12-28 | 2003-07-18 | Toshiba Corp | 部分ｓｏｉウェーハの製造方法、半導体装置及びその製造方法 |
| US20030123279A1 (en) * | 2002-01-03 | 2003-07-03 | International Business Machines Corporation | Silicon-on-insulator SRAM cells with increased stability and yield |
| DE10204871A1 (de) * | 2002-02-06 | 2003-08-21 | Infineon Technologies Ag | Kondensatorlose 1-Transistor-DRAM-Zelle und Herstellungsverfahren |
| US6661042B2 (en) | 2002-03-11 | 2003-12-09 | Monolithic System Technology, Inc. | One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region |
| JP4880867B2 (ja) * | 2002-04-10 | 2012-02-22 | セイコーインスツル株式会社 | 薄膜メモリ、アレイとその動作方法および製造方法 |
| JP3962638B2 (ja) | 2002-06-18 | 2007-08-22 | 株式会社東芝 | 半導体記憶装置、及び、半導体装置 |
| US6888200B2 (en) * | 2002-08-30 | 2005-05-03 | Micron Technology Inc. | One transistor SOI non-volatile random access memory cell |
| US6903969B2 (en) * | 2002-08-30 | 2005-06-07 | Micron Technology Inc. | One-device non-volatile random access memory cell |
| US6917078B2 (en) * | 2002-08-30 | 2005-07-12 | Micron Technology Inc. | One transistor SOI non-volatile random access memory cell |
| JP4044401B2 (ja) | 2002-09-11 | 2008-02-06 | 株式会社東芝 | 半導体記憶装置 |
| JP2004111643A (ja) * | 2002-09-18 | 2004-04-08 | Toshiba Corp | 半導体記憶装置、及び、その制御方法 |
| US7030436B2 (en) * | 2002-12-04 | 2006-04-18 | Micron Technology, Inc. | Embedded DRAM gain memory cell having MOS transistor body provided with a bi-polar transistor charge injecting means |
| US6714436B1 (en) | 2003-03-20 | 2004-03-30 | Motorola, Inc. | Write operation for capacitorless RAM |
| US6909151B2 (en) * | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
| US6897098B2 (en) * | 2003-07-28 | 2005-05-24 | Intel Corporation | Method of fabricating an ultra-narrow channel semiconductor device |
| US20050062088A1 (en) * | 2003-09-22 | 2005-03-24 | Texas Instruments Incorporated | Multi-gate one-transistor dynamic random access memory |
| US7072205B2 (en) * | 2003-11-19 | 2006-07-04 | Intel Corporation | Floating-body DRAM with two-phase write |
| US7002842B2 (en) * | 2003-11-26 | 2006-02-21 | Intel Corporation | Floating-body dynamic random access memory with purge line |
| US6952376B2 (en) * | 2003-12-22 | 2005-10-04 | Intel Corporation | Method and apparatus to generate a reference value in a memory array |
| JP4559728B2 (ja) * | 2003-12-26 | 2010-10-13 | 株式会社東芝 | 半導体記憶装置 |
| US6992339B2 (en) * | 2003-12-31 | 2006-01-31 | Intel Corporation | Asymmetric memory cell |
| US6903984B1 (en) * | 2003-12-31 | 2005-06-07 | Intel Corporation | Floating-body DRAM using write word line for increased retention time |
| US7001811B2 (en) * | 2003-12-31 | 2006-02-21 | Intel Corporation | Method for making memory cell without halo implant |
-
2004
- 2004-09-15 US US10/941,692 patent/US7184298B2/en active Active
- 2004-09-23 AT AT04787565T patent/ATE366983T1/de not_active IP Right Cessation
- 2004-09-23 EP EP04787565A patent/EP1671331B1/de active Active
- 2004-09-23 WO PCT/IB2004/003721 patent/WO2005029499A2/en active IP Right Grant
- 2004-09-23 DE DE602004007536T patent/DE602004007536T2/de active Active
-
2006
- 2006-01-17 US US11/334,338 patent/US7177175B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| ATE366983T1 (de) | 2007-08-15 |
| DE602004007536T2 (de) | 2008-03-20 |
| EP1671331A2 (de) | 2006-06-21 |
| US7184298B2 (en) | 2007-02-27 |
| EP1671331B1 (de) | 2007-07-11 |
| US20050063224A1 (en) | 2005-03-24 |
| US20060114717A1 (en) | 2006-06-01 |
| US7177175B2 (en) | 2007-02-13 |
| WO2005029499A2 (en) | 2005-03-31 |
| WO2005029499A3 (en) | 2005-06-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE602004007536D1 (de) | Stromarme programmiertechnik für einen schwebkörper-speichertransistor, speicherzelle und speichermatrix | |
| WO2007098044A3 (en) | Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same | |
| ATE267447T1 (de) | Programmierverfahren für einen nichtflüchtigen halbleiterspeicher | |
| WO2005055243A3 (en) | Low voltage eeprom memory arrays with isolated wells for each colum | |
| TW200802381A (en) | Self-boosting method for flash memory cells | |
| ATE348389T1 (de) | Segmentierte metall bitleitungen | |
| EP0991080A3 (de) | Nichtflüchtige Halbleiterspeicheranordnung | |
| TW200735107A (en) | Memory devices including floating body transistor capacitorless memory cells and related methods | |
| US20060239072A1 (en) | Nonvolatile memory device and semiconductor device | |
| TW200703579A (en) | Nonvolatile semiconductor memory | |
| NO20052450L (no) | Flashminne-arkitektur med avkodingsplan for sletting i sidemodus ved hjelp av NMOS og PMOS radarkoding | |
| TW200701237A (en) | Reference scheme for a non-volatile semiconductor memory device | |
| TW200623118A (en) | Nonvolatile ferroelectric memory device | |
| TW200638517A (en) | Method for fabricating semiconductor device | |
| WO2007087097A3 (en) | Nonvolatile memory and method of program inhibition | |
| WO2008004179A3 (en) | Non-volatile memory and-array and method for operating the game | |
| JP4047001B2 (ja) | 不揮発性半導体メモリ装置、そのローカルロウデコーダ構造、及び半導体メモリ装置、同装置でのワードライン駆動方法 | |
| DE60316449D1 (de) | Nichtflüchtige speicherarrayarchitektur mit kontaktloser separater p-mulde mit gleichförmiger tunnelung (cusp), herstellung und betrieb | |
| TW200505009A (en) | Byte-operational nonvolatile semiconductor memory device | |
| CN103794248B (zh) | 多栅极存储器的控制栅极字线驱动器电路 | |
| TW200711136A (en) | Multi-purpose semiconductor device | |
| TW200507288A (en) | A semiconductor memory device including the MOS transistor comprising the floating gate and the control gate | |
| WO2006138086A3 (en) | Non-volatile two-transistor programmable logic cell and array layout | |
| JP2000021183A (ja) | 半導体不揮発性メモリ | |
| CN100379026C (zh) | 沙漏随机访问存储器 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8327 | Change in the person/name/address of the patent owner |
Owner name: INNOVATIVE SILICON ISI SA, ECUBLENS, CH |
|
| R082 | Change of representative |
Ref document number: 1671331 Country of ref document: EP Representative=s name: EISENFUEHR, SPEISER & PARTNER, 28217 BREMEN, DE Ref document number: 1671331 Country of ref document: EP Representative=s name: MARKS & CLERK (LUXEMBOURG) LLP, LUXEMBOURG, LU |
|
| R082 | Change of representative |
Ref document number: 1671331 Country of ref document: EP Representative=s name: MARKS & CLERK (LUXEMBOURG) LLP, LUXEMBOURG, LU |