DE602004009821D1 - Halbleiterbauelement und Herstellungsverfahren dafür - Google Patents

Halbleiterbauelement und Herstellungsverfahren dafür

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Publication number
DE602004009821D1
DE602004009821D1 DE602004009821T DE602004009821T DE602004009821D1 DE 602004009821 D1 DE602004009821 D1 DE 602004009821D1 DE 602004009821 T DE602004009821 T DE 602004009821T DE 602004009821 T DE602004009821 T DE 602004009821T DE 602004009821 D1 DE602004009821 D1 DE 602004009821D1
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Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
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Active
Application number
DE602004009821T
Other languages
English (en)
Other versions
DE602004009821T2 (de
Inventor
Shinji Wakisaka
Hiroyasu Jobetto
Takeshi Wakabayashi
Ichiro Mihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2003379547A external-priority patent/JP4379693B2/ja
Priority claimed from JP2003395313A external-priority patent/JP4321758B2/ja
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Publication of DE602004009821D1 publication Critical patent/DE602004009821D1/de
Application granted granted Critical
Publication of DE602004009821T2 publication Critical patent/DE602004009821T2/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
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    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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US7692282B2 (en) 2010-04-06
TWI278048B (en) 2007-04-01
EP1683198A2 (de) 2006-07-26
WO2005045902A3 (en) 2005-08-18
DE602004009821T2 (de) 2008-03-06
TW200529338A (en) 2005-09-01
USRE43380E1 (en) 2012-05-15
US7563640B2 (en) 2009-07-21
US20080006943A1 (en) 2008-01-10
WO2005045902A2 (en) 2005-05-19
US7368813B2 (en) 2008-05-06
KR100727540B1 (ko) 2007-06-14
US20050140021A1 (en) 2005-06-30

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