DE602004023275D1 - Mehrfachauslösepunkt-schmelzverbindungs-latch-einrichtung und testverfahren der schmelzverbindung - Google Patents

Mehrfachauslösepunkt-schmelzverbindungs-latch-einrichtung und testverfahren der schmelzverbindung

Info

Publication number
DE602004023275D1
DE602004023275D1 DE602004023275T DE602004023275T DE602004023275D1 DE 602004023275 D1 DE602004023275 D1 DE 602004023275D1 DE 602004023275 T DE602004023275 T DE 602004023275T DE 602004023275 T DE602004023275 T DE 602004023275T DE 602004023275 D1 DE602004023275 D1 DE 602004023275D1
Authority
DE
Germany
Prior art keywords
melting
test method
latch device
point
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004023275T
Other languages
English (en)
Inventor
Gunther Lehmann
Norman Robson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE602004023275D1 publication Critical patent/DE602004023275D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
DE602004023275T 2003-01-21 2004-01-21 Mehrfachauslösepunkt-schmelzverbindungs-latch-einrichtung und testverfahren der schmelzverbindung Expired - Lifetime DE602004023275D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/347,727 US6882202B2 (en) 2003-01-21 2003-01-21 Multiple trip point fuse latch device and method
PCT/EP2004/000453 WO2004066309A1 (en) 2003-01-21 2004-01-21 Multiple trip point fuse latch device and test method of the fuse

Publications (1)

Publication Number Publication Date
DE602004023275D1 true DE602004023275D1 (de) 2009-11-05

Family

ID=32712396

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004023275T Expired - Lifetime DE602004023275D1 (de) 2003-01-21 2004-01-21 Mehrfachauslösepunkt-schmelzverbindungs-latch-einrichtung und testverfahren der schmelzverbindung

Country Status (6)

Country Link
US (1) US6882202B2 (de)
EP (1) EP1586098B1 (de)
JP (1) JP4128597B2 (de)
CN (1) CN100474454C (de)
DE (1) DE602004023275D1 (de)
WO (1) WO2004066309A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6975945B2 (en) * 2003-08-26 2005-12-13 Hewlett Packard Development Company, L.P. System and method for indication of fuse defects based upon analysis of fuse test data
US7196682B2 (en) * 2003-09-29 2007-03-27 Wintek Corporation Driving apparatus and method for active matrix organic light emitting display
US7379491B2 (en) * 2003-12-24 2008-05-27 Intel Corporation Flop repeater circuit
JP2006059429A (ja) * 2004-08-19 2006-03-02 Matsushita Electric Ind Co Ltd 半導体記憶装置
US7190629B2 (en) * 2005-02-08 2007-03-13 Micron Technology, Inc. Circuit and method for reading an antifuse
US20070268062A1 (en) * 2006-05-17 2007-11-22 Etron Technology, Inc. Fuse circuit for repair and detection
US20080211513A1 (en) * 2007-02-15 2008-09-04 Stmicroelectronics, Inc. Initiation of fuse sensing circuitry and storage of sensed fuse status information
KR101102776B1 (ko) * 2008-02-13 2012-01-05 매그나칩 반도체 유한회사 비휘발성 메모리 소자의 단위 셀 및 이를 구비한 비휘발성메모리 소자
US8736278B2 (en) * 2011-07-29 2014-05-27 Tessera Inc. System and method for testing fuse blow reliability for integrated circuits
JP2013101744A (ja) * 2012-12-27 2013-05-23 Fujitsu Semiconductor Ltd ヒューズ素子読み出し回路
KR102135168B1 (ko) * 2014-06-30 2020-07-17 에스케이하이닉스 주식회사 집적회로
CN109412557A (zh) * 2017-08-17 2019-03-01 三星电子株式会社 具有单个预充电节点的触发器

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5345110A (en) * 1993-04-13 1994-09-06 Micron Semiconductor, Inc. Low-power fuse detect and latch circuit
US5789970A (en) 1995-09-29 1998-08-04 Intel Corporation Static, low current, low voltage sensing circuit for sensing the state of a fuse device
US5631862A (en) 1996-03-05 1997-05-20 Micron Technology, Inc. Self current limiting antifuse circuit
JP3274364B2 (ja) 1996-08-14 2002-04-15 株式会社東芝 半導体装置及びヒューズチェック方法
KR100321169B1 (ko) 1998-06-30 2002-05-13 박종섭 앤티퓨즈의프로그래밍회로
JP3401522B2 (ja) * 1998-07-06 2003-04-28 日本電気株式会社 ヒューズ回路及び冗長デコーダ回路
US6204708B1 (en) * 1998-10-29 2001-03-20 Microchip Technology Incorporated Apparatus and method for an improved master-slave flip-flop with non-overlapping clocks
US6191629B1 (en) * 1999-09-27 2001-02-20 Conexant Systems, Inc. Interlaced master-slave ECL D flip-flop
JP4552266B2 (ja) * 2000-04-14 2010-09-29 エルピーダメモリ株式会社 半導体集積回路装置
JP3636965B2 (ja) 2000-05-10 2005-04-06 エルピーダメモリ株式会社 半導体装置
US6201750B1 (en) 2000-06-21 2001-03-13 International Business Machines Corporation Scannable fuse latches
US6426911B1 (en) 2000-10-19 2002-07-30 Infineon Technologies Ag Area efficient method for programming electrical fuses
US6373771B1 (en) 2001-01-17 2002-04-16 International Business Machines Corporation Integrated fuse latch and shift register for efficient programming and fuse readout
US6434077B1 (en) 2001-03-13 2002-08-13 Mosaid Technologies, Inc. Method and apparatus for selectively disabling logic in a semiconductor device
JP3857573B2 (ja) * 2001-11-20 2006-12-13 富士通株式会社 ヒューズ回路

Also Published As

Publication number Publication date
WO2004066309A1 (en) 2004-08-05
US20040140835A1 (en) 2004-07-22
CN1742344A (zh) 2006-03-01
JP4128597B2 (ja) 2008-07-30
US6882202B2 (en) 2005-04-19
CN100474454C (zh) 2009-04-01
EP1586098A1 (de) 2005-10-19
JP2006515100A (ja) 2006-05-18
EP1586098B1 (de) 2009-09-23

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