DE602004031925D1 - Asynchrone system-on-a-chip-verbindung - Google Patents

Asynchrone system-on-a-chip-verbindung

Info

Publication number
DE602004031925D1
DE602004031925D1 DE602004031925T DE602004031925T DE602004031925D1 DE 602004031925 D1 DE602004031925 D1 DE 602004031925D1 DE 602004031925 T DE602004031925 T DE 602004031925T DE 602004031925 T DE602004031925 T DE 602004031925T DE 602004031925 D1 DE602004031925 D1 DE 602004031925D1
Authority
DE
Germany
Prior art keywords
clock domain
asynchronous
synchronous
converters
domain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004031925T
Other languages
English (en)
Inventor
Uri Cummings
Andrew Lines
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fulcrum Microsystems Inc
Original Assignee
Fulcrum Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fulcrum Microsystems Inc filed Critical Fulcrum Microsystems Inc
Publication of DE602004031925D1 publication Critical patent/DE602004031925D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/005—Correction by an elastic buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/0004—Selecting arrangements using crossbar selectors in the switching stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H04L2012/5674—Synchronisation, timing recovery or alignment
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13034—A/D conversion, code compression/expansion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13214—Clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13322—Integrated circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13361—Synchronous systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13362—Asynchronous systems
DE602004031925T 2003-02-03 2004-01-26 Asynchrone system-on-a-chip-verbindung Expired - Lifetime DE602004031925D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US44482003P 2003-02-03 2003-02-03
US10/634,597 US7239669B2 (en) 2002-04-30 2003-08-04 Asynchronous system-on-a-chip interconnect
PCT/US2004/002216 WO2004070781A2 (en) 2003-02-03 2004-01-26 Asynchronous system-on-a-chip interconnect

Publications (1)

Publication Number Publication Date
DE602004031925D1 true DE602004031925D1 (de) 2011-05-05

Family

ID=32776255

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004031925T Expired - Lifetime DE602004031925D1 (de) 2003-02-03 2004-01-26 Asynchrone system-on-a-chip-verbindung

Country Status (5)

Country Link
US (2) US7239669B2 (de)
EP (1) EP1590835B1 (de)
AT (1) ATE503329T1 (de)
DE (1) DE602004031925D1 (de)
WO (1) WO2004070781A2 (de)

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Also Published As

Publication number Publication date
ATE503329T1 (de) 2011-04-15
US7239669B2 (en) 2007-07-03
EP1590835A2 (de) 2005-11-02
WO2004070781A2 (en) 2004-08-19
US20060239392A1 (en) 2006-10-26
EP1590835B1 (de) 2011-03-23
US20040151209A1 (en) 2004-08-05
EP1590835A4 (de) 2008-10-08
WO2004070781A3 (en) 2005-06-09

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