DE602006009001D1 - Identification eines Problembereichs in einem Maskenlayout unter Verwendung von einem Prozessempfindlichkeitmodells - Google Patents

Identification eines Problembereichs in einem Maskenlayout unter Verwendung von einem Prozessempfindlichkeitmodells

Info

Publication number
DE602006009001D1
DE602006009001D1 DE602006009001T DE602006009001T DE602006009001D1 DE 602006009001 D1 DE602006009001 D1 DE 602006009001D1 DE 602006009001 T DE602006009001 T DE 602006009001T DE 602006009001 T DE602006009001 T DE 602006009001T DE 602006009001 D1 DE602006009001 D1 DE 602006009001D1
Authority
DE
Germany
Prior art keywords
model
target
problem area
mask layout
sensitivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006009001T
Other languages
English (en)
Inventor
Lawrence S Melvin Iii
James P Shiely
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Synopsys Inc
Original Assignee
Synopsys Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Synopsys Inc filed Critical Synopsys Inc
Publication of DE602006009001D1 publication Critical patent/DE602006009001D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/705—Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Electron Beam Exposure (AREA)
DE602006009001T 2005-02-24 2006-01-20 Identification eines Problembereichs in einem Maskenlayout unter Verwendung von einem Prozessempfindlichkeitmodells Active DE602006009001D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/065,409 US7251807B2 (en) 2005-02-24 2005-02-24 Method and apparatus for identifying a manufacturing problem area in a layout using a process-sensitivity model

Publications (1)

Publication Number Publication Date
DE602006009001D1 true DE602006009001D1 (de) 2009-10-22

Family

ID=35999476

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006009001T Active DE602006009001D1 (de) 2005-02-24 2006-01-20 Identification eines Problembereichs in einem Maskenlayout unter Verwendung von einem Prozessempfindlichkeitmodells

Country Status (9)

Country Link
US (4) US7251807B2 (de)
EP (1) EP1696269B1 (de)
JP (1) JP4925408B2 (de)
KR (1) KR101190399B1 (de)
CN (2) CN1828613B (de)
AT (1) ATE442610T1 (de)
DE (1) DE602006009001D1 (de)
SG (1) SG125169A1 (de)
TW (2) TWI450115B (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7251807B2 (en) * 2005-02-24 2007-07-31 Synopsys, Inc. Method and apparatus for identifying a manufacturing problem area in a layout using a process-sensitivity model
US7475382B2 (en) * 2005-02-24 2009-01-06 Synopsys, Inc. Method and apparatus for determining an improved assist feature configuration in a mask layout
US7315999B2 (en) * 2005-03-17 2008-01-01 Synopsys, Inc. Method and apparatus for identifying assist feature placement problems
US7496880B2 (en) * 2005-03-17 2009-02-24 Synopsys, Inc. Method and apparatus for assessing the quality of a process model
US7458059B2 (en) * 2005-10-31 2008-11-25 Synopsys, Inc. Model of sensitivity of a simulated layout to a change in original layout, and use of model in proximity correction
US7840287B2 (en) * 2006-04-13 2010-11-23 Fisher-Rosemount Systems, Inc. Robust process model identification in model based control techniques
EP1862857B1 (de) * 2006-05-31 2012-08-08 Synopsys, Inc. Verfahren und Vorrichtung zum Bestimmen eines Prozessmodells für die Herstellung integrierter Schaltungen
US7743357B2 (en) * 2006-05-31 2010-06-22 Synopsys, Inc. Method and apparatus for determining a process model that models the impact of CAR/PEB on the resist profile
US7454739B2 (en) 2006-05-31 2008-11-18 Synopsys, Inc. Method and apparatus for determining an accurate photolithography process model
JP2010532511A (ja) * 2007-07-06 2010-10-07 サガンテック イスラエル リミテッド 固定及び自由レイアウトエンティティを含む回路レイアウトを修正するためのレイアウト修正エンジン
TW200929412A (en) * 2007-12-18 2009-07-01 Airoha Tech Corp Model modification method for a semiconductor device
US8120767B2 (en) * 2008-03-13 2012-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Mask making decision for manufacturing (DFM) on mask quality control
JP2009282319A (ja) * 2008-05-22 2009-12-03 Toshiba Corp パターン検証方法、パターン検証システム、パターン検証プログラム、マスク製造方法、および半導体装置の製造方法
KR101749987B1 (ko) 2008-06-03 2017-06-22 에이에스엠엘 네델란즈 비.브이. 모델-기반 공정 시뮬레이션 시스템들 및 방법들
US8117568B2 (en) * 2008-09-25 2012-02-14 International Business Machines Corporation Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit design
JP4762288B2 (ja) * 2008-09-26 2011-08-31 株式会社東芝 パターン形成不良領域算出方法
US8181128B2 (en) * 2008-10-13 2012-05-15 Synopsys, Inc. Method and apparatus for determining a photolithography process model which models the influence of topography variations
US7954071B2 (en) * 2008-10-31 2011-05-31 Synopsys, Inc. Assist feature placement based on a focus-sensitive cost-covariance field
NL2003718A (en) * 2008-11-10 2010-05-11 Brion Tech Inc Methods and system for model-based generic matching and tuning.
US8136054B2 (en) * 2009-01-29 2012-03-13 Synopsys, Inc. Compact abbe's kernel generation using principal component analysis
US8010913B2 (en) * 2009-04-14 2011-08-30 Synopsys, Inc. Model-based assist feature placement using inverse imaging approach
US9448706B2 (en) * 2009-07-29 2016-09-20 Synopsys, Inc. Loop removal in electronic design automation
US8694930B2 (en) * 2011-08-11 2014-04-08 Infineon Technologies Ag Method and apparatus for providing a layout defining a structure to be patterned onto a substrate
US8510699B1 (en) 2012-03-09 2013-08-13 International Business Machines Corporation Performance driven layout optimization using morphing of a basis set of representative layouts
US10365557B2 (en) * 2013-02-24 2019-07-30 Synopsys, Inc. Compact OPC model generation using virtual data
TWI621957B (zh) * 2013-03-14 2018-04-21 新納普系統股份有限公司 使用點擊最佳化的次解析度輔助特徵實現方式
CN103405164B (zh) * 2013-07-23 2015-08-12 山东科技大学 烤箱与烤盘配合布局的方法
EP3105637A1 (de) * 2014-02-11 2016-12-21 ASML Netherlands B.V. Modell zur berechnung einer stochastischen variation bei einem arbiträren muster
EP2952964A1 (de) * 2014-06-03 2015-12-09 Aselta Nanographics Verfahren zum Bestimmen von Parametern eines IC-Herstellungsverfahrens durch ein differenzielles Verfahren
WO2016008711A1 (en) 2014-07-14 2016-01-21 Asml Netherlands B.V. Optimization of assist features and source
KR102084048B1 (ko) 2014-10-02 2020-03-03 에이에스엠엘 네델란즈 비.브이. 어시스트 피처들의 규칙-기반 배치
KR102028712B1 (ko) 2015-04-10 2019-10-04 에이에스엠엘 네델란즈 비.브이. 검사와 계측을 위한 방법 및 장치
US10394116B2 (en) 2017-09-06 2019-08-27 International Business Machines Corporation Semiconductor fabrication design rule loophole checking for design for manufacturability optimization
US10621295B2 (en) 2018-04-10 2020-04-14 International Business Machines Corporation Incorporation of process variation contours in design rule and risk estimation aspects of design for manufacturability to increase fabrication yield
CN109596638B (zh) * 2018-10-26 2022-05-06 中国科学院光电研究院 有图形晶圆及掩模版的缺陷检测方法及装置
CN112904662B (zh) * 2021-05-07 2021-07-23 南京晶驱集成电路有限公司 辅助图形的添加方法、装置及测试版图

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6474547A (en) 1987-09-14 1989-03-20 Motorola Inc Manufacture of semiconductor for compensating strain between pattern on semiconductor body and mask for obtaining pattern
JPH04216548A (ja) * 1990-12-18 1992-08-06 Mitsubishi Electric Corp フォトマスク
JP3223718B2 (ja) * 1994-09-07 2001-10-29 松下電器産業株式会社 マスクデータの作成方法
US5774177A (en) * 1996-09-11 1998-06-30 Milliken Research Corporation Textile fabric inspection system
US5965309A (en) * 1997-08-28 1999-10-12 International Business Machines Corporation Focus or exposure dose parameter control system using tone reversing patterns
US6183919B1 (en) * 1999-06-11 2001-02-06 International Business Machines Corporation Darkfield imaging for enhancing optical detection of edges and minimum features
US6539521B1 (en) * 2000-09-29 2003-03-25 Numerical Technologies, Inc. Dissection of corners in a fabrication layout for correcting proximity effects
US6453457B1 (en) * 2000-09-29 2002-09-17 Numerical Technologies, Inc. Selection of evaluation point locations based on proximity effects model amplitudes for correcting proximity effects in a fabrication layout
EP1337838B1 (de) * 2000-11-30 2007-01-10 SIGMA-C Software AG Verfahren und vorrichtung zur bestimmung von eigenschaften einer integrierten schaltung
US6873720B2 (en) * 2001-03-20 2005-03-29 Synopsys, Inc. System and method of providing mask defect printability analysis
JP4748343B2 (ja) * 2001-04-26 2011-08-17 大日本印刷株式会社 ウエーハ転写検証方法
TW520544B (en) * 2001-06-15 2003-02-11 United Microelectronics Corp Method and apparatus for measuring bridge caused by mask layout correction
DE10143723B4 (de) 2001-08-31 2006-09-28 Infineon Technologies Ag Verfahren zur Optimierung eines Layouts für eine Maske zur Verwendung bei der Halbleiterherstellung
US6673638B1 (en) * 2001-11-14 2004-01-06 Kla-Tencor Corporation Method and apparatus for the production of process sensitive lithographic features
US20030121021A1 (en) * 2001-12-26 2003-06-26 Numerical Technologies, Inc. System and method for determining manufacturing error enhancement factor
US6904587B2 (en) * 2002-12-20 2005-06-07 Synopsys, Inc. Incremental lithography mask layout design and verification
US6964032B2 (en) * 2003-02-28 2005-11-08 International Business Machines Corporation Pitch-based subresolution assist feature design
US6934930B2 (en) * 2003-07-08 2005-08-23 Texas Instruments Incorporated Generating an optical model for lens aberrations
JP4684584B2 (ja) 2003-07-23 2011-05-18 キヤノン株式会社 マスク及びその製造方法、並びに、露光方法
JP2005099765A (ja) * 2003-08-28 2005-04-14 Toshiba Corp プロセス近接効果の予測モデルの作成方法、工程の管理方法、半導体装置の製造方法、フォトマスクの製造方法およびプログラム
US6978438B1 (en) * 2003-10-01 2005-12-20 Advanced Micro Devices, Inc. Optical proximity correction (OPC) technique using generalized figure of merit for photolithograhic processing
US7451068B2 (en) * 2003-10-10 2008-11-11 Synopsys, Inc. Method and apparatus for generating an OPC segmentation based on modeled intensity gradients
US7251807B2 (en) * 2005-02-24 2007-07-31 Synopsys, Inc. Method and apparatus for identifying a manufacturing problem area in a layout using a process-sensitivity model
US7475382B2 (en) * 2005-02-24 2009-01-06 Synopsys, Inc. Method and apparatus for determining an improved assist feature configuration in a mask layout
US7315999B2 (en) * 2005-03-17 2008-01-01 Synopsys, Inc. Method and apparatus for identifying assist feature placement problems

Also Published As

Publication number Publication date
US20060190913A1 (en) 2006-08-24
US20060190912A1 (en) 2006-08-24
KR101190399B1 (ko) 2012-10-12
CN1828613B (zh) 2011-05-18
CN1825323A (zh) 2006-08-30
TW200639668A (en) 2006-11-16
JP2006235600A (ja) 2006-09-07
CN100541498C (zh) 2009-09-16
US20060190914A1 (en) 2006-08-24
US7243332B2 (en) 2007-07-10
EP1696269B1 (de) 2009-09-09
JP4925408B2 (ja) 2012-04-25
SG125169A1 (en) 2006-09-29
US7784018B2 (en) 2010-08-24
US20070250804A1 (en) 2007-10-25
EP1696269A2 (de) 2006-08-30
ATE442610T1 (de) 2009-09-15
CN1828613A (zh) 2006-09-06
US7320119B2 (en) 2008-01-15
KR20060094470A (ko) 2006-08-29
TWI325547B (en) 2010-06-01
TW201017460A (en) 2010-05-01
TWI450115B (zh) 2014-08-21
US7251807B2 (en) 2007-07-31
EP1696269A3 (de) 2008-01-23

Similar Documents

Publication Publication Date Title
ATE442610T1 (de) Identification eines problembereichs in einem maskenlayout unter verwendung von einem prozessempfindlichkeitmodells
ATE525677T1 (de) Verfahren und vorrichtung zur bestimmung einer verbesserten konfiguration von hilfsstrukturen in einem maskenlayout
SE0702459L (sv) Diagnostisk och i prognostisk metod samt tillhörande system
TW200632719A (en) Multivariate control of semiconductor processes
EP1376422A3 (de) System und Vorrichtung zum Risiko-Management in einem Projekt
ATE436054T1 (de) Systeme und verfahren zur validierung von vorlagen
DE602006012292D1 (de) Verfahren zur datenverarbeitung mit modularer potenzierung und dazugehörige vorrichtung
SG113598A1 (en) Method of manufacturing reliability checking and verification for lithography process using a calibrated eigen decomposition model
TW200720851A (en) Dense OPC
ATE468572T1 (de) System und verfahren zur erkennung verformbarer objekte
DE602005019162D1 (de) Tragbare vorrichtung
ATE546794T1 (de) System, verfahren und computerprogramm zur frühen ereigniserkennung
ATE542185T1 (de) Verfahren zur bewirkung von transaktionen auf ticket-basis unter verwendung eines armbands
EA200700394A1 (ru) Способ, устройство и система визуализации вероятностных моделей
WO2005081910A3 (en) Generalization of the photo process window and its application to opc test pattern design
TW200607002A (en) Analysis method, exposing equipment and exposing equipment system
TW200734810A (en) Method and apparatus for evaluating photomask, and method for manufacturing semiconductor device
ATE433124T1 (de) System und verfahren zum analysieren von radarinformationen
SG169372A1 (en) Method and system for evaluating a variation in a parameter of a pattern
DE602007002474D1 (de) Verfahren und Datenbanksystem zur Durchführung einer XML-Datenbankabfrage
ATE433591T1 (de) Authentifizierungsverfahren für einen gegenstand oder stoff durch markierung oder chemische verfolgbarkeit
ATE507512T1 (de) Verfahren, computerprogramm mit programmcode- mitteln und computerprogramm-produkt zur analyse von einflussgrössen auf einen brennvorgang in einer brennkammer unter verwendung eines trainierbaren, statistischen modells
DE602006016924D1 (de) Rfid-kennzeichnung und verfahren zur herstellung einer rfid-kennzeichnung
DE502007004879D1 (de) Verfahren zur gewinnung von werkstückausschnitten aus einem plattenartigen werkstück
ATE532072T1 (de) Verfahren und vorrichtung zur beurteilung von polypeptidaggregation

Legal Events

Date Code Title Description
8364 No opposition during term of opposition