DE602006012674D1 - Halbleitervorrichtung und dazugehörige Montagestruktur - Google Patents

Halbleitervorrichtung und dazugehörige Montagestruktur

Info

Publication number
DE602006012674D1
DE602006012674D1 DE602006012674T DE602006012674T DE602006012674D1 DE 602006012674 D1 DE602006012674 D1 DE 602006012674D1 DE 602006012674 T DE602006012674 T DE 602006012674T DE 602006012674 T DE602006012674 T DE 602006012674T DE 602006012674 D1 DE602006012674 D1 DE 602006012674D1
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Germany
Prior art keywords
semiconductor device
mounting structure
associated mounting
semiconductor
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006012674T
Other languages
English (en)
Inventor
Takeshi Wakabayashi
Ichiro Mihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
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Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Publication of DE602006012674D1 publication Critical patent/DE602006012674D1/de
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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DE602006012674T 2005-06-01 2006-05-30 Halbleitervorrichtung und dazugehörige Montagestruktur Active DE602006012674D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005161026A JP4449824B2 (ja) 2005-06-01 2005-06-01 半導体装置およびその実装構造
PCT/JP2006/311166 WO2006129832A1 (en) 2005-06-01 2006-05-30 Semiconductor device and mounting structure thereof

Publications (1)

Publication Number Publication Date
DE602006012674D1 true DE602006012674D1 (de) 2010-04-15

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DE602006012674T Active DE602006012674D1 (de) 2005-06-01 2006-05-30 Halbleitervorrichtung und dazugehörige Montagestruktur

Country Status (7)

Country Link
US (1) US7719116B2 (de)
EP (1) EP1897138B1 (de)
JP (1) JP4449824B2 (de)
KR (1) KR100877018B1 (de)
CN (1) CN100514627C (de)
DE (1) DE602006012674D1 (de)
WO (1) WO2006129832A1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
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US8552559B2 (en) * 2004-07-29 2013-10-08 Megica Corporation Very thick metal interconnection scheme in IC chips
JP4449824B2 (ja) * 2005-06-01 2010-04-14 カシオ計算機株式会社 半導体装置およびその実装構造
JP4193897B2 (ja) 2006-05-19 2008-12-10 カシオ計算機株式会社 半導体装置およびその製造方法
US8022552B2 (en) 2006-06-27 2011-09-20 Megica Corporation Integrated circuit and method for fabricating the same
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EP1897138B1 (de) 2010-03-03
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WO2006129832A1 (en) 2006-12-07
US20060273463A1 (en) 2006-12-07
KR20070088688A (ko) 2007-08-29
CN101091250A (zh) 2007-12-19
JP4449824B2 (ja) 2010-04-14
KR100877018B1 (ko) 2009-01-07
EP1897138A1 (de) 2008-03-12
CN100514627C (zh) 2009-07-15

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