DE602006018178D1 - Schaltkreis und verfahren zur unterteilung einer camram-bank durch steuerung einer virtuellen masse - Google Patents

Schaltkreis und verfahren zur unterteilung einer camram-bank durch steuerung einer virtuellen masse

Info

Publication number
DE602006018178D1
DE602006018178D1 DE602006018178T DE602006018178T DE602006018178D1 DE 602006018178 D1 DE602006018178 D1 DE 602006018178D1 DE 602006018178 T DE602006018178 T DE 602006018178T DE 602006018178 T DE602006018178 T DE 602006018178T DE 602006018178 D1 DE602006018178 D1 DE 602006018178D1
Authority
DE
Germany
Prior art keywords
circuit
sub
cam
banks
bank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006018178T
Other languages
English (en)
Inventor
Michael Thaithanh Phan
Chiaming Chai
Jeffrey Todd Bridges
Jeffrey Herbert Fischer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of DE602006018178D1 publication Critical patent/DE602006018178D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
DE602006018178T 2005-10-28 2006-10-30 Schaltkreis und verfahren zur unterteilung einer camram-bank durch steuerung einer virtuellen masse Active DE602006018178D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/262,062 US7242600B2 (en) 2005-10-28 2005-10-28 Circuit and method for subdividing a CAMRAM bank by controlling a virtual ground
PCT/US2006/060370 WO2007051204A1 (en) 2005-10-28 2006-10-30 Circuit and method for subdividing a camram bank by controlling a virtual ground

Publications (1)

Publication Number Publication Date
DE602006018178D1 true DE602006018178D1 (de) 2010-12-23

Family

ID=37847007

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006018178T Active DE602006018178D1 (de) 2005-10-28 2006-10-30 Schaltkreis und verfahren zur unterteilung einer camram-bank durch steuerung einer virtuellen masse

Country Status (10)

Country Link
US (1) US7242600B2 (de)
EP (1) EP1941513B1 (de)
JP (2) JP5096353B2 (de)
KR (1) KR100958222B1 (de)
CN (1) CN101346775B (de)
AT (1) ATE488010T1 (de)
DE (1) DE602006018178D1 (de)
IL (1) IL191128A0 (de)
TW (1) TWI308755B (de)
WO (1) WO2007051204A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7796418B2 (en) * 2008-03-19 2010-09-14 Broadcom Corporation Programmable memory cell
US8837188B1 (en) * 2011-06-23 2014-09-16 Netlogic Microsystems, Inc. Content addressable memory row having virtual ground and charge sharing
US8773880B2 (en) 2011-06-23 2014-07-08 Netlogic Microsystems, Inc. Content addressable memory array having virtual ground nodes
US8654555B2 (en) * 2012-06-04 2014-02-18 Raytheon Company ROIC control signal generator
JP6392082B2 (ja) 2014-10-31 2018-09-19 ルネサスエレクトロニクス株式会社 半導体記憶装置
US10289752B2 (en) * 2016-12-12 2019-05-14 Intel Corporation Accelerator for gather-update-scatter operations including a content-addressable memory (CAM) and CAM controller
US11158373B2 (en) 2019-06-11 2021-10-26 Micron Technology, Inc. Apparatuses, systems, and methods for determining extremum numerical values
US10964378B2 (en) * 2019-08-22 2021-03-30 Micron Technology, Inc. Apparatus and method including analog accumulator for determining row access rate and target row address used for refresh operation
US11967377B2 (en) * 2021-01-08 2024-04-23 Mediatek Singapore Pte. Ltd. Dynamically gated search lines for low-power multi-stage content addressable memory

Family Cites Families (17)

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Publication number Priority date Publication date Assignee Title
JPS58122693A (ja) * 1982-01-14 1983-07-21 Nippon Telegr & Teleph Corp <Ntt> メモリ回路
JPH0746506B2 (ja) * 1985-09-30 1995-05-17 株式会社東芝 半導体メモリ装置
JPH0421997A (ja) * 1990-05-16 1992-01-24 Nec Corp 連想記憶回路
JPH0438797A (ja) * 1990-06-04 1992-02-07 Kawasaki Steel Corp 連想メモリの比較回路
JPH04182993A (ja) * 1990-11-19 1992-06-30 Toshiba Corp 連想メモリセル
JPH087580A (ja) * 1994-06-23 1996-01-12 Hitachi Ltd 半導体記憶装置および情報処理装置
JP2836596B2 (ja) * 1996-08-02 1998-12-14 日本電気株式会社 連想メモリ
US5796650A (en) * 1997-05-19 1998-08-18 Lsi Logic Corporation Memory circuit including write control unit wherein subthreshold leakage may be reduced
JP3095064B2 (ja) * 1997-09-08 2000-10-03 日本電気株式会社 連想記憶装置
JP3190868B2 (ja) * 1997-11-21 2001-07-23 エヌイーシーマイクロシステム株式会社 連想メモリ装置
US5986923A (en) * 1998-05-06 1999-11-16 Hewlett-Packard Company Method and apparatus for improving read/write stability of a single-port SRAM cell
WO2002059896A1 (en) * 2001-01-26 2002-08-01 Koninklijke Philips Electronics N.V. Power saving semi-conductor integrated circuit
US6700827B2 (en) * 2001-02-08 2004-03-02 Integrated Device Technology, Inc. Cam circuit with error correction
JP2004164395A (ja) * 2002-11-14 2004-06-10 Renesas Technology Corp アドレス変換装置
US7019999B1 (en) * 2003-10-08 2006-03-28 Netlogic Microsystems, Inc Content addressable memory with latching sense amplifier
KR100604876B1 (ko) * 2004-07-02 2006-07-31 삼성전자주식회사 다양한 ｐｖｔ 변화에 대해서도 안정적인 버츄얼 레일스킴을 적용한 ｓｒａｍ 장치
US7050318B1 (en) * 2004-10-01 2006-05-23 Netlogic Microsystems, Inc. Selective match line pre-charging in a CAM device using pre-compare operations

Also Published As

Publication number Publication date
WO2007051204A1 (en) 2007-05-03
EP1941513B1 (de) 2010-11-10
TWI308755B (en) 2009-04-11
JP2013012287A (ja) 2013-01-17
TW200731262A (en) 2007-08-16
US7242600B2 (en) 2007-07-10
ATE488010T1 (de) 2010-11-15
KR100958222B1 (ko) 2010-05-17
JP2009514139A (ja) 2009-04-02
US20070097722A1 (en) 2007-05-03
IL191128A0 (en) 2008-12-29
EP1941513A1 (de) 2008-07-09
KR20080068896A (ko) 2008-07-24
CN101346775B (zh) 2012-04-18
JP5096353B2 (ja) 2012-12-12
CN101346775A (zh) 2009-01-14

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