DE602008003985D1 - Verfahren zur Herstellung einer mehrschichtigen Leiterplatte - Google Patents

Verfahren zur Herstellung einer mehrschichtigen Leiterplatte

Info

Publication number
DE602008003985D1
DE602008003985D1 DE602008003985T DE602008003985T DE602008003985D1 DE 602008003985 D1 DE602008003985 D1 DE 602008003985D1 DE 602008003985 T DE602008003985 T DE 602008003985T DE 602008003985 T DE602008003985 T DE 602008003985T DE 602008003985 D1 DE602008003985 D1 DE 602008003985D1
Authority
DE
Germany
Prior art keywords
producing
circuit board
printed circuit
multilayer printed
multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602008003985T
Other languages
English (en)
Inventor
Yoshihiro Machida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Publication of DE602008003985D1 publication Critical patent/DE602008003985D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10234—Metallic balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305—Moulding and encapsulation
    • H05K2203/1327—Moulding over PCB locally or completely
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/167—Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
DE602008003985T 2007-02-07 2008-02-06 Verfahren zur Herstellung einer mehrschichtigen Leiterplatte Active DE602008003985D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007028521A JP4842167B2 (ja) 2007-02-07 2007-02-07 多層配線基板の製造方法

Publications (1)

Publication Number Publication Date
DE602008003985D1 true DE602008003985D1 (de) 2011-02-03

Family

ID=39432845

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602008003985T Active DE602008003985D1 (de) 2007-02-07 2008-02-06 Verfahren zur Herstellung einer mehrschichtigen Leiterplatte

Country Status (7)

Country Link
US (1) US7624501B2 (de)
EP (1) EP1956878B1 (de)
JP (1) JP4842167B2 (de)
KR (1) KR20080074030A (de)
CN (1) CN101242714A (de)
DE (1) DE602008003985D1 (de)
TW (1) TW200845862A (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7602062B1 (en) * 2005-08-10 2009-10-13 Altera Corporation Package substrate with dual material build-up layers
JP5157455B2 (ja) * 2006-01-16 2013-03-06 日本電気株式会社 半導体装置
JP4073945B1 (ja) * 2007-01-12 2008-04-09 新光電気工業株式会社 多層配線基板の製造方法
JP2009099624A (ja) * 2007-10-12 2009-05-07 Fujitsu Ltd 配線基板およびその製造方法
US8030752B2 (en) * 2007-12-18 2011-10-04 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing semiconductor package and semiconductor plastic package using the same
JP2009206154A (ja) * 2008-02-26 2009-09-10 Nec Electronics Corp 配線基板、及びその製造方法
JP5172590B2 (ja) * 2008-10-14 2013-03-27 新光電気工業株式会社 積層配線基板の樹脂封止方法及び樹脂封止装置
JP2010186848A (ja) * 2009-02-12 2010-08-26 Fujitsu Ltd 電子部品ユニットの製造方法
US8829355B2 (en) * 2009-03-27 2014-09-09 Ibiden Co., Ltd. Multilayer printed wiring board
US20120039712A1 (en) 2009-05-08 2012-02-16 Yasuo Ueno Vertical axis wind turbine device
JP5206630B2 (ja) * 2009-08-27 2013-06-12 日立電線株式会社 フレキシブルハーネスを用いた電気的接続部品及び電気的接続方法
TWI442530B (zh) * 2009-10-14 2014-06-21 Advanced Semiconductor Eng 封裝載板、封裝結構以及封裝載板製程
JP5718342B2 (ja) * 2009-10-16 2015-05-13 エンパイア テクノロジー ディベロップメント エルエルシー 半導体ウェーハにフィルムを付加する装置および方法ならびに半導体ウェーハを処理する方法
KR101128559B1 (ko) * 2010-09-13 2012-03-23 삼성전기주식회사 인쇄회로기판의 비아홀 형성방법
US9059187B2 (en) * 2010-09-30 2015-06-16 Ibiden Co., Ltd. Electronic component having encapsulated wiring board and method for manufacturing the same
JP5715835B2 (ja) * 2011-01-25 2015-05-13 新光電気工業株式会社 半導体パッケージ及びその製造方法
US8780576B2 (en) * 2011-09-14 2014-07-15 Invensas Corporation Low CTE interposer
US9040837B2 (en) * 2011-12-14 2015-05-26 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US20130256885A1 (en) * 2012-04-03 2013-10-03 Conexant Systems, Inc. Copper Sphere Array Package
US20140008110A1 (en) * 2012-07-03 2014-01-09 Apple Incl Pcb manufacturing process and structure
US8969730B2 (en) * 2012-08-16 2015-03-03 Apple Inc. Printed circuit solder connections
JP6166265B2 (ja) * 2012-09-10 2017-07-19 株式会社メイコー 部品内蔵基板及びその製造方法
TWI563606B (en) * 2014-01-29 2016-12-21 Siliconware Precision Industries Co Ltd Package substrate as well as manufacturing method thereof and semiconductor package as well as manufacturing method thereof
JP6570924B2 (ja) * 2015-08-31 2019-09-04 新光電気工業株式会社 電子部品装置及びその製造方法
CN109661125B (zh) * 2017-10-12 2021-11-16 宏启胜精密电子(秦皇岛)有限公司 电路板及其制作方法
DE112018006091T5 (de) 2017-12-27 2020-08-20 Murata Manufacturing Co., Ltd. Halbleiter-verbund-bauelement und darin verwendete package-platine
JP7251951B2 (ja) * 2018-11-13 2023-04-04 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
CN111240518B (zh) * 2020-01-13 2023-09-29 合肥维信诺科技有限公司 显示面板及显示装置
CN114727516A (zh) * 2021-01-05 2022-07-08 庆鼎精密电子（淮安）有限公司 多层电路板及其制作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146674A (en) * 1991-07-01 1992-09-15 International Business Machines Corporation Manufacturing process of a high density substrate design
DE69218319T2 (de) * 1991-07-26 1997-07-10 Nec Corp Mehrschichtige Leiterplatte aus Polyimid und Verfahren zur Herstellung
JP3198796B2 (ja) * 1993-06-25 2001-08-13 富士電機株式会社 モールドモジュール
US5523628A (en) * 1994-08-05 1996-06-04 Hughes Aircraft Company Apparatus and method for protecting metal bumped integrated circuit chips during processing and for providing mechanical support to interconnected chips
US6545226B2 (en) * 2001-05-31 2003-04-08 International Business Machines Corporation Printed wiring board interposer sub-assembly
US6573460B2 (en) * 2001-09-20 2003-06-03 Dpac Technologies Corp Post in ring interconnect using for 3-D stacking
JP2003318545A (ja) * 2002-04-22 2003-11-07 Sony Corp 多層型プリント配線基板及び多層型プリント配線基板の製造方法
JP4004880B2 (ja) 2002-07-12 2007-11-07 大日本印刷株式会社 多層配線板の製造方法
JP2004172473A (ja) * 2002-11-21 2004-06-17 Fujikura Ltd 多層プリント配線板およびその製造方法
JP2004221335A (ja) * 2003-01-15 2004-08-05 Fujikura Ltd 多層配線基板及びその製造方法
WO2004103039A1 (ja) * 2003-05-19 2004-11-25 Dai Nippon Printing Co., Ltd. 両面配線基板および両面配線基板の製造方法並びに多層配線基板
JP4700332B2 (ja) * 2003-12-05 2011-06-15 イビデン株式会社 多層プリント配線板
JP2006210766A (ja) * 2005-01-31 2006-08-10 Sumitomo Electric Ind Ltd 多層プリント配線板の製造方法及び多層プリント配線板
JP4073945B1 (ja) * 2007-01-12 2008-04-09 新光電気工業株式会社 多層配線基板の製造方法

Also Published As

Publication number Publication date
EP1956878A3 (de) 2009-11-04
CN101242714A (zh) 2008-08-13
US7624501B2 (en) 2009-12-01
JP4842167B2 (ja) 2011-12-21
KR20080074030A (ko) 2008-08-12
EP1956878A2 (de) 2008-08-13
JP2008192999A (ja) 2008-08-21
US20080184555A1 (en) 2008-08-07
EP1956878B1 (de) 2010-12-22
TW200845862A (en) 2008-11-16

Similar Documents

Publication Publication Date Title
DE602008003985D1 (de) Verfahren zur Herstellung einer mehrschichtigen Leiterplatte
DE602007009603D1 (de) Verfahren zur Herstellung einer mehrschichtigen Leiterplatte
DE602006008455D1 (de) Verfahren zur herstellung einer polyimidfolie
EP2259668A4 (de) Verfahren zur herstellung einer mehrschichtigen leiterplatte
TWI365685B (en) Method for manufacturing printed wiring board
DE602004026257D1 (de) Verfahren zur Herstellung einer flexiblen Leiterplatte
EP2200413A4 (de) Mehrschichtige bestückte leiterplatte und verfahren zur herstellung einer mehrschichtigen bestückten leiterplatte
DE602008005947D1 (de) Leiterplatte und Verfahren zu deren Herstellung
EP2209358A4 (de) Mehrschichtige bestückte leiterplatte und verfahren zur herstellung einer mehrschichtigen bestückten leiterplatte
EP2381748A4 (de) Leiterplatte und verfahren zu ihrer herstellung
EP2357877A4 (de) Leiterplatte und verfahren zu ihrer herstellung
DE602006011671D1 (de) Verfahren zur Herstellung eines mehrschichtigen Keramiksubstrats
EP2280594A4 (de) Leiterplatte und verfahren zu ihrer herstellung
DE602007010373D1 (de) Verfahren zur Herstellung einer Wabenstruktur
EP1978795A4 (de) Verfahren zur herstellung einer leiterplatte
EP1835792A4 (de) Verfahren zur herstellung einer leiterplatte
EP2278396A4 (de) Lichtempfindliche harzzusammensetzung, lichtempfindliches element, verfahren zur herstellung einer resiststruktur und verfahren zur herstellung einer leiterplatte
DE602005001595D1 (de) Verfahren zur Herstellung einer Leiterplatte
EP2141971A4 (de) Mehrschichtige leiterplatte und verfahren zu ihrer herstellung
ATE526429T1 (de) Verfahren zur herstellung einer beschichtung
DE602005012169D1 (de) Verfahren zur Herstellung eines keramischen Mehrschichtbauelements
DE102004047045A8 (de) Verfahren zur Herstellung einer gedruckten Leiterplatte in paralleler Weise
DE602009000860D1 (de) Verfahren zur Herstellung dreidimensionaler Flüssigkristallpolymer-Mehrschichtleiterplatten
DE602006006758D1 (de) Verfahren zur Herstellung einer Zahnstange
AT503190A3 (de) Verfahren zur herstellung einer halbleitervorrichtung