DE602009000556D1 - Herstellungsverfahren von einem SOI-Transistor mit selbstjustierter Grundplatte und Gate und mit einer vergrabenen Oxidschicht mit veränderlicher Dicke - Google Patents
Herstellungsverfahren von einem SOI-Transistor mit selbstjustierter Grundplatte und Gate und mit einer vergrabenen Oxidschicht mit veränderlicher DickeInfo
- Publication number
- DE602009000556D1 DE602009000556D1 DE602009000556T DE602009000556T DE602009000556D1 DE 602009000556 D1 DE602009000556 D1 DE 602009000556D1 DE 602009000556 T DE602009000556 T DE 602009000556T DE 602009000556 T DE602009000556 T DE 602009000556T DE 602009000556 D1 DE602009000556 D1 DE 602009000556D1
- Authority
- DE
- Germany
- Prior art keywords
- layer
- baseplate
- aligned
- self
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 125000002524 organometallic group Chemical group 0.000 abstract 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 238000000151 deposition Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0853868A FR2932609B1 (fr) | 2008-06-11 | 2008-06-11 | Transistor soi avec plan de masse et grille auto-alignes et oxyde enterre d'epaisseur variable |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602009000556D1 true DE602009000556D1 (de) | 2011-02-24 |
Family
ID=40328960
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602009000556T Active DE602009000556D1 (de) | 2008-06-11 | 2009-06-09 | Herstellungsverfahren von einem SOI-Transistor mit selbstjustierter Grundplatte und Gate und mit einer vergrabenen Oxidschicht mit veränderlicher Dicke |
Country Status (5)
Country | Link |
---|---|
US (1) | US7910419B2 (de) |
EP (1) | EP2133919B1 (de) |
AT (1) | ATE495551T1 (de) |
DE (1) | DE602009000556D1 (de) |
FR (1) | FR2932609B1 (de) |
Families Citing this family (58)
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US8236661B2 (en) * | 2009-09-28 | 2012-08-07 | International Business Machines Corporation | Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage |
US8421162B2 (en) | 2009-09-30 | 2013-04-16 | Suvolta, Inc. | Advanced transistors with punch through suppression |
US8273617B2 (en) | 2009-09-30 | 2012-09-25 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
US20110079861A1 (en) * | 2009-09-30 | 2011-04-07 | Lucian Shifren | Advanced Transistors with Threshold Voltage Set Dopant Structures |
US8530286B2 (en) | 2010-04-12 | 2013-09-10 | Suvolta, Inc. | Low power semiconductor transistor structure and method of fabrication thereof |
US8569128B2 (en) | 2010-06-21 | 2013-10-29 | Suvolta, Inc. | Semiconductor structure and method of fabrication thereof with mixed metal types |
US8759872B2 (en) | 2010-06-22 | 2014-06-24 | Suvolta, Inc. | Transistor with threshold voltage set notch and method of fabrication thereof |
US8929054B2 (en) * | 2010-07-21 | 2015-01-06 | Cleanvolt Energy, Inc. | Use of organic and organometallic high dielectric constant material for improved energy storage devices and associated methods |
US8618554B2 (en) | 2010-11-08 | 2013-12-31 | International Business Machines Corporation | Method to reduce ground-plane poisoning of extremely-thin SOI (ETSOI) layer with thin buried oxide |
US8404551B2 (en) | 2010-12-03 | 2013-03-26 | Suvolta, Inc. | Source/drain extension control for advanced transistors |
US8461875B1 (en) | 2011-02-18 | 2013-06-11 | Suvolta, Inc. | Digital circuits having improved transistors, and methods therefor |
US8525271B2 (en) | 2011-03-03 | 2013-09-03 | Suvolta, Inc. | Semiconductor structure with improved channel stack and method for fabrication thereof |
US8400219B2 (en) | 2011-03-24 | 2013-03-19 | Suvolta, Inc. | Analog circuits having improved transistors, and methods therefor |
US8748270B1 (en) | 2011-03-30 | 2014-06-10 | Suvolta, Inc. | Process for manufacturing an improved analog transistor |
US8999861B1 (en) | 2011-05-11 | 2015-04-07 | Suvolta, Inc. | Semiconductor structure with substitutional boron and method for fabrication thereof |
US8796048B1 (en) | 2011-05-11 | 2014-08-05 | Suvolta, Inc. | Monitoring and measurement of thin film layers |
US8811068B1 (en) | 2011-05-13 | 2014-08-19 | Suvolta, Inc. | Integrated circuit devices and methods |
US8569156B1 (en) | 2011-05-16 | 2013-10-29 | Suvolta, Inc. | Reducing or eliminating pre-amorphization in transistor manufacture |
US8735987B1 (en) | 2011-06-06 | 2014-05-27 | Suvolta, Inc. | CMOS gate stack structures and processes |
US8995204B2 (en) | 2011-06-23 | 2015-03-31 | Suvolta, Inc. | Circuit devices and methods having adjustable transistor body bias |
US8629016B1 (en) | 2011-07-26 | 2014-01-14 | Suvolta, Inc. | Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer |
WO2013022753A2 (en) | 2011-08-05 | 2013-02-14 | Suvolta, Inc. | Semiconductor devices having fin structures and fabrication methods thereof |
US8748986B1 (en) | 2011-08-05 | 2014-06-10 | Suvolta, Inc. | Electronic device with controlled threshold voltage |
US8614128B1 (en) | 2011-08-23 | 2013-12-24 | Suvolta, Inc. | CMOS structures and processes based on selective thinning |
US8645878B1 (en) | 2011-08-23 | 2014-02-04 | Suvolta, Inc. | Porting a circuit design from a first semiconductor process to a second semiconductor process |
US8713511B1 (en) | 2011-09-16 | 2014-04-29 | Suvolta, Inc. | Tools and methods for yield-aware semiconductor manufacturing process target generation |
US9236466B1 (en) | 2011-10-07 | 2016-01-12 | Mie Fujitsu Semiconductor Limited | Analog circuits having improved insulated gate transistors, and methods therefor |
US8895327B1 (en) | 2011-12-09 | 2014-11-25 | Suvolta, Inc. | Tipless transistors, short-tip transistors, and methods and circuits therefor |
US8819603B1 (en) | 2011-12-15 | 2014-08-26 | Suvolta, Inc. | Memory circuits and methods of making and designing the same |
US8883600B1 (en) | 2011-12-22 | 2014-11-11 | Suvolta, Inc. | Transistor having reduced junction leakage and methods of forming thereof |
US8599623B1 (en) | 2011-12-23 | 2013-12-03 | Suvolta, Inc. | Circuits and methods for measuring circuit elements in an integrated circuit device |
US8877619B1 (en) | 2012-01-23 | 2014-11-04 | Suvolta, Inc. | Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom |
US8970289B1 (en) | 2012-01-23 | 2015-03-03 | Suvolta, Inc. | Circuits and devices for generating bi-directional body bias voltages, and methods therefor |
US9093550B1 (en) | 2012-01-31 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same |
US9406567B1 (en) | 2012-02-28 | 2016-08-02 | Mie Fujitsu Semiconductor Limited | Method for fabricating multiple transistor devices on a substrate with varying threshold voltages |
US8863064B1 (en) | 2012-03-23 | 2014-10-14 | Suvolta, Inc. | SRAM cell layout structure and devices therefrom |
US9299698B2 (en) | 2012-06-27 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Semiconductor structure with multiple transistors having various threshold voltages |
US8836037B2 (en) | 2012-08-13 | 2014-09-16 | International Business Machines Corporation | Structure and method to form input/output devices |
US8637955B1 (en) | 2012-08-31 | 2014-01-28 | Suvolta, Inc. | Semiconductor structure with reduced junction leakage and method of fabrication thereof |
US9112057B1 (en) | 2012-09-18 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Semiconductor devices with dopant migration suppression and method of fabrication thereof |
US9041126B2 (en) | 2012-09-21 | 2015-05-26 | Mie Fujitsu Semiconductor Limited | Deeply depleted MOS transistors having a screening layer and methods thereof |
US9431068B2 (en) | 2012-10-31 | 2016-08-30 | Mie Fujitsu Semiconductor Limited | Dynamic random access memory (DRAM) with low variation transistor peripheral circuits |
US8816754B1 (en) | 2012-11-02 | 2014-08-26 | Suvolta, Inc. | Body bias circuits and methods |
CN103811349A (zh) * | 2012-11-06 | 2014-05-21 | 中国科学院微电子研究所 | 半导体结构及其制造方法 |
US9093997B1 (en) | 2012-11-15 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Slew based process and bias monitors and related methods |
US9070477B1 (en) | 2012-12-12 | 2015-06-30 | Mie Fujitsu Semiconductor Limited | Bit interleaved low voltage static random access memory (SRAM) and related methods |
US9112484B1 (en) | 2012-12-20 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit process and bias monitors and related methods |
US9268885B1 (en) | 2013-02-28 | 2016-02-23 | Mie Fujitsu Semiconductor Limited | Integrated circuit device methods and models with predicted device metric variations |
US9299801B1 (en) | 2013-03-14 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Method for fabricating a transistor device with a tuned dopant profile |
US8889541B1 (en) | 2013-05-07 | 2014-11-18 | International Business Machines Corporation | Reduced short channel effect of III-V field effect transistor via oxidizing aluminum-rich underlayer |
US9478571B1 (en) | 2013-05-24 | 2016-10-25 | Mie Fujitsu Semiconductor Limited | Buried channel deeply depleted channel transistor |
US9431339B2 (en) | 2014-02-19 | 2016-08-30 | International Business Machines Corporation | Wiring structure for trench fuse component with methods of fabrication |
US9311442B2 (en) | 2014-04-25 | 2016-04-12 | Globalfoundries Inc. | Net-voltage-aware optical proximity correction (OPC) |
US9710006B2 (en) | 2014-07-25 | 2017-07-18 | Mie Fujitsu Semiconductor Limited | Power up body bias circuits and methods |
US9319013B2 (en) | 2014-08-19 | 2016-04-19 | Mie Fujitsu Semiconductor Limited | Operational amplifier input offset correction with transistor threshold voltage adjustment |
US9423563B2 (en) | 2014-10-20 | 2016-08-23 | International Business Machines Corporation | Variable buried oxide thickness for a waveguide |
EP3236503A1 (de) * | 2016-04-18 | 2017-10-25 | IMEC vzw | Verfahren zur herstellung von vollständig selbstjustierten dünnfilmtransistoren mit doppel-gate |
US10217707B2 (en) * | 2016-09-16 | 2019-02-26 | International Business Machines Corporation | Trench contact resistance reduction |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR920008834A (ko) * | 1990-10-09 | 1992-05-28 | 아이자와 스스무 | 박막 반도체 장치 |
JP3462301B2 (ja) * | 1995-06-16 | 2003-11-05 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
US5923067A (en) * | 1997-04-04 | 1999-07-13 | International Business Machines Corporation | 3-D CMOS-on-SOI ESD structure and method |
US6072217A (en) * | 1998-06-11 | 2000-06-06 | Sun Microsystems, Inc. | Tunable threshold SOI device using isolated well structure for back gate |
FR2829294B1 (fr) * | 2001-09-03 | 2004-10-15 | Commissariat Energie Atomique | Transistor a effet de champ a grilles auto-alignees horizontales et procede de fabrication d'un tel transistor |
JP3764401B2 (ja) * | 2002-04-18 | 2006-04-05 | 株式会社東芝 | 半導体装置の製造方法 |
JP4256381B2 (ja) * | 2005-11-09 | 2009-04-22 | 株式会社東芝 | 半導体装置 |
JP4525928B2 (ja) * | 2005-12-27 | 2010-08-18 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
-
2008
- 2008-06-11 FR FR0853868A patent/FR2932609B1/fr not_active Expired - Fee Related
-
2009
- 2009-06-09 EP EP09162258A patent/EP2133919B1/de not_active Not-in-force
- 2009-06-09 DE DE602009000556T patent/DE602009000556D1/de active Active
- 2009-06-09 AT AT09162258T patent/ATE495551T1/de not_active IP Right Cessation
- 2009-06-11 US US12/483,037 patent/US7910419B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP2133919A1 (de) | 2009-12-16 |
ATE495551T1 (de) | 2011-01-15 |
EP2133919B1 (de) | 2011-01-12 |
US7910419B2 (en) | 2011-03-22 |
FR2932609A1 (fr) | 2009-12-18 |
US20090311834A1 (en) | 2009-12-17 |
FR2932609B1 (fr) | 2010-12-24 |
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