DE60205118D1 - Integriertes prüfen eines serialisierers/deserialisierers in fpga - Google Patents

Integriertes prüfen eines serialisierers/deserialisierers in fpga

Info

Publication number
DE60205118D1
DE60205118D1 DE60205118T DE60205118T DE60205118D1 DE 60205118 D1 DE60205118 D1 DE 60205118D1 DE 60205118 T DE60205118 T DE 60205118T DE 60205118 T DE60205118 T DE 60205118T DE 60205118 D1 DE60205118 D1 DE 60205118D1
Authority
DE
Germany
Prior art keywords
deserializer
serializer
fpga
integrated inspection
inspection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60205118T
Other languages
English (en)
Other versions
DE60205118T2 (de
Inventor
H Lesea
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Application granted granted Critical
Publication of DE60205118D1 publication Critical patent/DE60205118D1/de
Publication of DE60205118T2 publication Critical patent/DE60205118T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
DE60205118T 2001-07-24 2002-05-30 Integriertes prüfen eines serialisierers/deserialisierers in fpga Expired - Lifetime DE60205118T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/912,683 US6874107B2 (en) 2001-07-24 2001-07-24 Integrated testing of serializer/deserializer in FPGA
US912683 2001-07-24
PCT/US2002/017532 WO2003010550A2 (en) 2001-07-24 2002-05-30 Integrated testing of serializer/deserializer in fpga

Publications (2)

Publication Number Publication Date
DE60205118D1 true DE60205118D1 (de) 2005-08-25
DE60205118T2 DE60205118T2 (de) 2006-05-24

Family

ID=25432268

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60205118T Expired - Lifetime DE60205118T2 (de) 2001-07-24 2002-05-30 Integriertes prüfen eines serialisierers/deserialisierers in fpga

Country Status (6)

Country Link
US (1) US6874107B2 (de)
EP (1) EP1410053B1 (de)
JP (1) JP4056469B2 (de)
CA (1) CA2453601C (de)
DE (1) DE60205118T2 (de)
WO (1) WO2003010550A2 (de)

Families Citing this family (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7343535B2 (en) * 2002-02-06 2008-03-11 Avago Technologies General Ip Dte Ltd Embedded testing capability for integrated serializer/deserializers
KR100445636B1 (ko) * 2002-06-17 2004-08-25 삼성전자주식회사 에프피지에이와 다수개의 프로그램 가능한 메모리모듈들을 이용한 컴퓨터 시스템 테스트 장치 및 그 테스트방법
US7672340B2 (en) * 2002-08-06 2010-03-02 Broadcom Corporation Built-in-self test for high-speed serial bit stream multiplexing and demultiplexing chip set
US7082556B2 (en) * 2002-10-07 2006-07-25 Finisar Corporation System and method of detecting a bit processing error
TWI232308B (en) * 2003-01-24 2005-05-11 Benq Corp Test method and circuit for testing inter-device connections of field programmable gate arrays
US7062586B2 (en) * 2003-04-21 2006-06-13 Xilinx, Inc. Method and apparatus for communication within a programmable logic device using serial transceivers
US7065601B2 (en) * 2003-06-06 2006-06-20 Stmicroelectronics N.V. Interface for prototyping integrated systems
AU2003255533A1 (en) * 2003-07-15 2005-02-25 Agilent Technologies, Inc. Integrated circuit with bit error test capability
US7376917B1 (en) * 2003-08-25 2008-05-20 Xilinx, Inc. Client-server semiconductor verification system
US7281167B2 (en) * 2003-08-26 2007-10-09 Finisar Corporation Multi-purpose network diagnostic modules
US7188283B1 (en) * 2003-09-11 2007-03-06 Xilinx, Inc. Communication signal testing with a programmable logic device
US7885320B1 (en) 2003-09-11 2011-02-08 Xilinx, Inc. MGT/FPGA clock management system
US20050063648A1 (en) * 2003-09-19 2005-03-24 Wilson Robert Edward Alignment post for optical subassemblies made with cylindrical rods, tubes, spheres, or similar features
US7520679B2 (en) * 2003-09-19 2009-04-21 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Optical device package with turning mirror and alignment post
US20050063431A1 (en) * 2003-09-19 2005-03-24 Gallup Kendra J. Integrated optics and electronics
US6953990B2 (en) * 2003-09-19 2005-10-11 Agilent Technologies, Inc. Wafer-level packaging of optoelectronic devices
US6982437B2 (en) * 2003-09-19 2006-01-03 Agilent Technologies, Inc. Surface emitting laser package having integrated optical element and alignment post
US20050071730A1 (en) * 2003-09-30 2005-03-31 Lattice Semiconductor Corporation Continuous self-verify of configuration memory in programmable logic devices
US7587649B2 (en) * 2003-09-30 2009-09-08 Mentor Graphics Corporation Testing of reconfigurable logic and interconnect sources
US7218670B1 (en) * 2003-11-18 2007-05-15 Xilinx, Inc. Method of measuring the performance of a transceiver in a programmable logic device
US7135904B1 (en) * 2004-01-12 2006-11-14 Marvell Semiconductor Israel Ltd. Jitter producing circuitry and methods
US7454514B2 (en) * 2004-01-12 2008-11-18 Hewlett-Packard Development Company, L.P. Processing data with uncertain arrival time
US7842948B2 (en) 2004-02-27 2010-11-30 Nvidia Corporation Flip chip semiconductor die internal signal access system and method
US20050213995A1 (en) * 2004-03-26 2005-09-29 Myunghee Lee Low power and low jitter optical receiver for fiber optic communication link
US7091745B1 (en) * 2004-05-24 2006-08-15 Xilinx, Inc. Indicating completion of configuration for programmable devices
KR100607196B1 (ko) * 2004-07-05 2006-08-01 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 테스트 방법
US7279887B1 (en) * 2004-08-06 2007-10-09 Nvidia Corporation In-process system level test before surface mount
DE102004050402A1 (de) * 2004-10-15 2006-04-27 Marconi Communications Gmbh Verfahren und Vorrichtung zum Erkennen eines Störeffekts in einem Nachrichtenkanal
US7454675B1 (en) 2004-10-22 2008-11-18 Xilinx, Inc. Testing of a programmable device
US7376929B1 (en) 2004-11-10 2008-05-20 Xilinx, Inc. Method and apparatus for providing a protection circuit for protecting an integrated circuit design
US7216050B1 (en) * 2004-12-07 2007-05-08 Nvidia Corporation System and method for testing a printed circuit board assembly
US7434192B2 (en) * 2004-12-13 2008-10-07 Altera Corporation Techniques for optimizing design of a hard intellectual property block for data transmission
US7499513B1 (en) * 2004-12-23 2009-03-03 Xilinx, Inc. Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit
JP4811902B2 (ja) * 2004-12-24 2011-11-09 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置のテスト方法
US7257750B1 (en) 2005-01-13 2007-08-14 Lattice Semiconductor Corporation Self-verification of configuration memory in programmable logic devices
US7526033B2 (en) * 2005-02-04 2009-04-28 Agere Systems Inc. Serializer deserializer (SERDES) testing
EP1859289A4 (de) 2005-03-16 2011-03-30 Gaterocket Inc Fpga-emulationssystem
US7814336B1 (en) 2005-07-12 2010-10-12 Xilinx, Inc. Method and apparatus for protection of time-limited operation of a circuit
US7500156B2 (en) * 2005-09-28 2009-03-03 Electronics And Telecommunications Research Institute Method and apparatus for verifying multi-channel data
US20070121711A1 (en) * 2005-11-30 2007-05-31 Offord Glen E PLL with programmable jitter for loopback serdes testing and the like
US7596744B1 (en) 2006-02-24 2009-09-29 Lattice Semiconductor Corporation Auto recovery from volatile soft error upsets (SEUs)
US7627806B1 (en) * 2006-03-01 2009-12-01 Altera Corporation Integrated hard-wired or partly hard-wired CRC generation and/or checking architecture for a physical coding sublayer in a programmable logic device
US7539967B1 (en) 2006-05-05 2009-05-26 Altera Corporation Self-configuring components on a device
US8024639B2 (en) 2006-06-23 2011-09-20 Schweitzer Engineering Laboratories, Inc. Software and methods to detect and correct data structure
US20080080114A1 (en) * 2006-09-29 2008-04-03 Schweitzer Engineering Laboratories, Inc. Apparatus, systems and methods for reliably detecting faults within a power distribution system
KR100885294B1 (ko) * 2006-12-05 2009-02-23 한국전자통신연구원 다양한 데이터양을 가지는 고속데이터들간의 인터페이스변환 방법 및 장치
JP2008175646A (ja) 2007-01-17 2008-07-31 Nec Electronics Corp 半導体装置、半導体装置のテスト回路、及び試験方法
EP2360488B1 (de) 2007-03-20 2013-01-23 Rambus Inc. Integrierte Schaltung mit Empfängerjittertoleranzmessung
US8065574B1 (en) * 2007-06-08 2011-11-22 Lattice Semiconductor Corporation Soft error detection logic testing systems and methods
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
US8271252B2 (en) * 2007-11-08 2012-09-18 Nvidia Corporation Automatic verification of device models
US20090144595A1 (en) * 2007-11-30 2009-06-04 Mathstar, Inc. Built-in self-testing (bist) of field programmable object arrays
US8510616B2 (en) * 2008-02-14 2013-08-13 Nvidia Corporation Scalable scan-based test architecture with reduced test time and test power
US8745200B2 (en) * 2008-05-06 2014-06-03 Nvidia Corporation Testing operation of processors setup to operate in different modes
US8228972B2 (en) 2008-06-04 2012-07-24 Stmicroelectronics, Inc. SERDES with jitter-based built-in self test (BIST) for adapting FIR filter coefficients
US8943457B2 (en) * 2008-11-24 2015-01-27 Nvidia Corporation Simulating scan tests with reduced resources
US8433950B2 (en) * 2009-03-17 2013-04-30 International Business Machines Corporation System to determine fault tolerance in an integrated circuit and associated methods
US20100306437A1 (en) * 2009-05-26 2010-12-02 Heath Matthew W Method and apparatus to selectively extend an embedded microprocessor bus through a different external bus
US8386867B2 (en) 2009-07-02 2013-02-26 Silicon Image, Inc. Computer memory test structure
US8310383B2 (en) * 2009-12-30 2012-11-13 Jds Uniphase Corporation Generating a jittered digital signal using a serializer device
US8543873B2 (en) 2010-01-06 2013-09-24 Silicon Image, Inc. Multi-site testing of computer memory devices and serial IO ports
US8503593B2 (en) 2010-06-23 2013-08-06 Raytheon Company Waveform generator in a multi-chip system
US8319523B2 (en) 2010-06-23 2012-11-27 Raytheon Company Chip interface
US20120011423A1 (en) * 2010-07-10 2012-01-12 Mehdi Entezari Silent error detection in sram-based fpga devices
US8504882B2 (en) 2010-09-17 2013-08-06 Altera Corporation Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations
CN103140768B (zh) * 2010-08-13 2016-01-27 阿尔特拉公司 用于执行或者有助于示波器、抖动和/或误比特率测试器操作的集成电路上的电路系统
US8441768B2 (en) 2010-09-08 2013-05-14 Schweitzer Engineering Laboratories Inc Systems and methods for independent self-monitoring
US8761215B2 (en) * 2010-12-08 2014-06-24 Institut National D'optique Pulse shaping module and generator for use with a pulsed laser oscillator
JP2013085118A (ja) * 2011-10-07 2013-05-09 Fujitsu Ltd 伝送試験装置、伝送試験方法及び伝送試験プログラム
CN102495354B (zh) * 2011-12-30 2013-12-18 常州工学院 电路板测试系统的测试工作方法
GB201201596D0 (en) * 2012-01-31 2012-03-14 Texas Instruments Ltd Multi-lane alignment and de-skew circuit and algorithm
US9007731B2 (en) 2012-03-26 2015-04-14 Schweitzer Engineering Laboratories, Inc. Leveraging inherent redundancy in a multifunction IED
US9222981B2 (en) 2012-12-28 2015-12-29 Nvidia Corporation Global low power capture scheme for cores
US9395414B2 (en) 2012-12-28 2016-07-19 Nvidia Corporation System for reducing peak power during scan shift at the local level for scan based tests
US9377510B2 (en) 2012-12-28 2016-06-28 Nvidia Corporation System for reducing peak power during scan shift at the global level for scan based tests
US9411701B2 (en) * 2013-03-13 2016-08-09 Xilinx, Inc. Analog block and test blocks for testing thereof
JP6478562B2 (ja) 2013-11-07 2019-03-06 株式会社半導体エネルギー研究所 半導体装置
JP6393590B2 (ja) 2013-11-22 2018-09-19 株式会社半導体エネルギー研究所 半導体装置
JP6444723B2 (ja) 2014-01-09 2018-12-26 株式会社半導体エネルギー研究所 装置
US9379713B2 (en) 2014-01-17 2016-06-28 Semiconductor Energy Laboratory Co., Ltd. Data processing device and driving method thereof
JP2015165226A (ja) 2014-02-07 2015-09-17 株式会社半導体エネルギー研究所 装置
US9869716B2 (en) 2014-02-07 2018-01-16 Semiconductor Energy Laboratory Co., Ltd. Device comprising programmable logic element
CN105527564B (zh) * 2015-12-25 2017-07-04 中国南方电网有限责任公司电网技术研究中心 Fpga内部功能自诊断方法与系统
CN106780371A (zh) * 2016-11-29 2017-05-31 西安天圆光电科技有限公司 一种256×256元mos薄膜电阻阵驱动装置及驱动工作方法
US10234505B1 (en) 2017-02-27 2019-03-19 Xilinx, Inc. Clock generation for integrated circuit testing
US10067189B1 (en) 2017-03-20 2018-09-04 Xilinx, Inc. Input/output path testing and characterization using scan chains
US10812103B1 (en) 2018-02-23 2020-10-20 Xilinx, Inc. Cyclic redundancy check engine and method therefor
KR102512985B1 (ko) * 2018-06-12 2023-03-22 삼성전자주식회사 반도체 장치를 위한 테스트 장치 및 반도체 장치의 제조 방법
CN112055215A (zh) * 2020-07-27 2020-12-08 恒宇信通航空装备(北京)股份有限公司 一种基于fpga光纤视频处理方法
US11323362B2 (en) 2020-08-07 2022-05-03 Schweitzer Engineering Laboratories, Inc. Resilience to single event upsets in software defined networks
CN113985256A (zh) * 2021-11-01 2022-01-28 北京中科胜芯科技有限公司 一种fpga寿命试验方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US34363A (en) * 1862-02-11 Improvement in machinery for cleaning cotton
USRE34363E (en) 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US5671355A (en) * 1992-06-26 1997-09-23 Predacomm, Inc. Reconfigurable network interface apparatus and method
US5361373A (en) * 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US6006343A (en) * 1993-07-30 1999-12-21 Texas Instruments Incorporated Method and apparatus for streamlined testing of electrical circuits
GB9508932D0 (en) * 1995-05-02 1995-06-21 Xilinx Inc FPGA with parallel and serial user interfaces
US5793822A (en) 1995-10-16 1998-08-11 Symbios, Inc. Bist jitter tolerance measurement technique
US5991907A (en) 1996-02-02 1999-11-23 Lucent Technologies Inc. Method for testing field programmable gate arrays
US5790563A (en) 1996-02-05 1998-08-04 Lsi Logic Corp. Self test of core with unpredictable latency
US5742531A (en) 1996-05-03 1998-04-21 Xilinx Inc Configurable parallel and bit serial load apparatus
US5825201A (en) * 1996-06-21 1998-10-20 Quicklogic Corporation Programming architecture for a programmable integrated circuit employing antifuses
US6232845B1 (en) 1996-09-17 2001-05-15 Xilinx, Inc. Circuit for measuring signal delays in synchronous memory elements
US5914616A (en) 1997-02-26 1999-06-22 Xilinx, Inc. FPGA repeatable interconnect structure with hierarchical interconnect lines
US6020755A (en) * 1997-09-26 2000-02-01 Lucent Technologies Inc. Hybrid programmable gate arrays
US6167077A (en) * 1997-12-23 2000-12-26 Lsi Logic Corporation Using multiple high speed serial lines to transmit high data rates while compensating for overall skew
US6096091A (en) * 1998-02-24 2000-08-01 Advanced Micro Devices, Inc. Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip
US6191614B1 (en) * 1999-04-05 2001-02-20 Xilinx, Inc. FPGA configuration circuit including bus-based CRC register
US6295315B1 (en) * 1999-04-20 2001-09-25 Arnold M. Frisch Jitter measurement system and method

Also Published As

Publication number Publication date
US6874107B2 (en) 2005-03-29
CA2453601C (en) 2007-08-21
EP1410053B1 (de) 2005-07-20
WO2003010550A2 (en) 2003-02-06
EP1410053A2 (de) 2004-04-21
US20030023912A1 (en) 2003-01-30
WO2003010550A3 (en) 2003-05-15
DE60205118T2 (de) 2006-05-24
JP2004537054A (ja) 2004-12-09
CA2453601A1 (en) 2003-02-06
JP4056469B2 (ja) 2008-03-05

Similar Documents

Publication Publication Date Title
DE60205118D1 (de) Integriertes prüfen eines serialisierers/deserialisierers in fpga
LUC00127I1 (fr) Dacomitinib et ses derives pharmaceutiquement accepatbles ( vizimpro )
NL301115I2 (nl) Drospirenon in combinatie met estetrol
DE60222994D1 (de) Konfigurierbare messvorrichtung
GB0400683D0 (en) Boundary-scan testing of opto-electronic devices
NO20040657L (no) Gravetanntupp og -adapteranordning.
NO20025524L (no) Nedihulls måleanordning og -teknikk
DE60109214D1 (de) Gefässdichtungsgerät un gefässtrennungsgerät
DE60236010D1 (de) Kalibrierung der gewebedichte in der computertomographie
DE60239383D1 (de) Ic-karte und ic-kartenadapter
DE60109328D1 (de) Gefässdichtungsgerät und gefässtrennungsgerät
DE60229337D1 (de) Bildauswertungsverfahren und Mikroskop
EP1414005A4 (de) Inspektionsverfahren, halbleiterbauelement und anzeige
EP1651971A4 (de) Test-standard-schnittstellen und -architekturen
DE10196595T1 (de) Vorrichtung und Halbleiter-Prüfvorrichtung
ITMI20031127A0 (it) Anticorpi anti-hgf e loro uso
DE60229938D1 (de) ENTWICKLUNGSEINRICHTUNG UND BILDformungsgerät
DE50115721D1 (de) Koordinatenmessgerät
DE50212439D1 (de) Sensoranordnung, insbesondere mikromechanische sensoranordnung
GB0308070D0 (en) Integrated circuit design and testing
GB0020427D0 (en) Moem device and fabrication method
DE60137306D1 (de) Selbsttragendes und anpassbares Messgerät
DE60316990D1 (de) LSI-Testanordnung und Testverfahren
DE60112723D1 (de) Lssd schnittstelle
DE60131341D1 (de) Fülladapter

Legal Events

Date Code Title Description
8364 No opposition during term of opposition