DE60207303D1 - Speicherbusschnittstelle mit geringem energieverbrauch - Google Patents

Speicherbusschnittstelle mit geringem energieverbrauch

Info

Publication number
DE60207303D1
DE60207303D1 DE60207303T DE60207303T DE60207303D1 DE 60207303 D1 DE60207303 D1 DE 60207303D1 DE 60207303 T DE60207303 T DE 60207303T DE 60207303 T DE60207303 T DE 60207303T DE 60207303 D1 DE60207303 D1 DE 60207303D1
Authority
DE
Germany
Prior art keywords
memory bus
bus interface
power consumption
low power
response
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60207303T
Other languages
English (en)
Other versions
DE60207303T2 (de
Inventor
Jeffrey Wilcox
Noam Yosef
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE60207303D1 publication Critical patent/DE60207303D1/de
Application granted granted Critical
Publication of DE60207303T2 publication Critical patent/DE60207303T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3225—Monitoring of peripheral devices of memory devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3253—Power saving in bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
DE60207303T 2002-01-02 2002-12-31 Speicherbusschnittstelle mit geringem energieverbrauch Expired - Lifetime DE60207303T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/038,960 US7000065B2 (en) 2002-01-02 2002-01-02 Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and enabling sense amplifiers
US38960 2002-01-02
PCT/US2002/041742 WO2003058467A1 (en) 2002-01-02 2002-12-31 Power reduction in a memory bus interface

Publications (2)

Publication Number Publication Date
DE60207303D1 true DE60207303D1 (de) 2005-12-15
DE60207303T2 DE60207303T2 (de) 2006-03-30

Family

ID=21902905

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60207303T Expired - Lifetime DE60207303T2 (de) 2002-01-02 2002-12-31 Speicherbusschnittstelle mit geringem energieverbrauch

Country Status (9)

Country Link
US (3) US7000065B2 (de)
EP (1) EP1463998B1 (de)
KR (1) KR100611266B1 (de)
CN (1) CN1613065B (de)
AT (1) ATE309575T1 (de)
AU (1) AU2002360836A1 (de)
DE (1) DE60207303T2 (de)
TW (1) TWI279680B (de)
WO (1) WO2003058467A1 (de)

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US20040128416A1 (en) * 2002-12-11 2004-07-01 Tsvika Kurts Apparatus and method for address bus power control
US7216240B2 (en) * 2002-12-11 2007-05-08 Intel Corporation Apparatus and method for address bus power control
US7827424B2 (en) * 2004-07-29 2010-11-02 Ati Technologies Ulc Dynamic clock control circuit and method
US7782805B1 (en) 2005-02-08 2010-08-24 Med Belhadj High speed packet interface and method
US8593470B2 (en) * 2005-02-24 2013-11-26 Ati Technologies Ulc Dynamic memory clock switching circuit and method for adjusting power consumption
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KR101331569B1 (ko) 2005-04-21 2013-11-21 바이올린 메모리 인코포레이티드 상호접속 시스템
US7800621B2 (en) * 2005-05-16 2010-09-21 Ati Technologies Inc. Apparatus and methods for control of a memory controller
KR100656353B1 (ko) * 2005-07-12 2006-12-11 한국전자통신연구원 메모리 전력 소모를 줄이는 방법
US7945793B2 (en) * 2006-08-11 2011-05-17 Intel Corporation Interface frequency modulation to allow non-terminated operation and power reduction
US7730337B2 (en) * 2007-01-24 2010-06-01 Via Technologies, Inc. Method and apparatus for asserting a hardware pin to disable a data bus connecting a processor and a chipset during power saving state
US7605628B2 (en) * 2007-05-07 2009-10-20 Lsi Corporation System for glitch-free delay updates of a standard cell-based programmable delay
US8135972B2 (en) 2009-03-10 2012-03-13 Cortina Systems, Inc. Data interface power consumption control
US9465756B2 (en) * 2009-12-23 2016-10-11 Violin Memory Inc. Configurable interconnection system
US8799685B2 (en) 2010-08-25 2014-08-05 Advanced Micro Devices, Inc. Circuits and methods for providing adjustable power consumption
US8356155B2 (en) * 2010-09-13 2013-01-15 Advanced Micro Devices, Inc. Dynamic RAM Phy interface with configurable power states
US8966151B2 (en) * 2012-03-30 2015-02-24 Spansion Llc Apparatus and method for a reduced pin count (RPC) memory bus interface including a read data strobe signal
EP2845113B1 (de) * 2012-05-01 2016-04-06 Marvell World Trade Ltd. Systeme und verfahren für dqs-gating
US9658642B2 (en) 2013-07-01 2017-05-23 Intel Corporation Timing control for unmatched signal receiver
US10127100B2 (en) 2016-06-03 2018-11-13 International Business Machines Corporation Correcting a data storage error caused by a broken conductor using bit inversion
CN111240596A (zh) * 2020-01-14 2020-06-05 深圳市德名利电子有限公司 一种判断闪存的操作接口模式的方法和装置以及设备

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US6961787B2 (en) 2002-01-07 2005-11-01 Intel Corporation Method and apparatus for updating task files
US20040128416A1 (en) 2002-12-11 2004-07-01 Tsvika Kurts Apparatus and method for address bus power control
US7216240B2 (en) 2002-12-11 2007-05-08 Intel Corporation Apparatus and method for address bus power control
US7152167B2 (en) 2002-12-11 2006-12-19 Intel Corporation Apparatus and method for data bus power control
KR100704622B1 (ko) * 2004-09-24 2007-04-10 삼성전자주식회사 멀티스트리밍 오디오 제어를 위한 사용자 인터페이스제공방법 및 장치

Also Published As

Publication number Publication date
US20030126485A1 (en) 2003-07-03
AU2002360836A1 (en) 2003-07-24
DE60207303T2 (de) 2006-03-30
WO2003058467A1 (en) 2003-07-17
EP1463998A1 (de) 2004-10-06
TWI279680B (en) 2007-04-21
US20060190751A1 (en) 2006-08-24
US7000065B2 (en) 2006-02-14
CN1613065B (zh) 2010-05-26
CN1613065A (zh) 2005-05-04
KR20040070301A (ko) 2004-08-06
TW200301859A (en) 2003-07-16
ATE309575T1 (de) 2005-11-15
KR100611266B1 (ko) 2006-08-10
EP1463998B1 (de) 2005-11-09
US8176240B2 (en) 2012-05-08
US10102157B2 (en) 2018-10-16
US20130103867A1 (en) 2013-04-25

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Legal Events

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8364 No opposition during term of opposition