DE60217157D1 - Verfahren und vorrichtung zum binden von shadow-registern an vektorisierte interrupts - Google Patents

Verfahren und vorrichtung zum binden von shadow-registern an vektorisierte interrupts

Info

Publication number
DE60217157D1
DE60217157D1 DE60217157T DE60217157T DE60217157D1 DE 60217157 D1 DE60217157 D1 DE 60217157D1 DE 60217157 T DE60217157 T DE 60217157T DE 60217157 T DE60217157 T DE 60217157T DE 60217157 D1 DE60217157 D1 DE 60217157D1
Authority
DE
Germany
Prior art keywords
vectorized
interrupts
tabs
binding shadow
shadow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60217157T
Other languages
English (en)
Other versions
DE60217157T2 (de
Inventor
G Uhler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MIPS Tech LLC
Original Assignee
MIPS Technologies Inc
MIPS Tech LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MIPS Technologies Inc, MIPS Tech LLC filed Critical MIPS Technologies Inc
Application granted granted Critical
Publication of DE60217157D1 publication Critical patent/DE60217157D1/de
Publication of DE60217157T2 publication Critical patent/DE60217157T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4812Task transfer initiation or dispatching by interrupt, e.g. masked
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/3012Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling
DE60217157T 2001-10-12 2002-09-10 Verfahren und vorrichtung zum binden von shadow-registern an vektorisierte interrupts Expired - Lifetime DE60217157T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/977,084 US7487339B2 (en) 2001-10-12 2001-10-12 Method and apparatus for binding shadow registers to vectored interrupts
US977084 2001-10-12
PCT/US2002/028893 WO2003048946A2 (en) 2001-10-12 2002-09-10 Method and apparatus for binding shadow registers to vectored interrupts

Publications (2)

Publication Number Publication Date
DE60217157D1 true DE60217157D1 (de) 2007-02-08
DE60217157T2 DE60217157T2 (de) 2007-10-04

Family

ID=25524795

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60217157T Expired - Lifetime DE60217157T2 (de) 2001-10-12 2002-09-10 Verfahren und vorrichtung zum binden von shadow-registern an vektorisierte interrupts

Country Status (5)

Country Link
US (4) US7487339B2 (de)
EP (2) EP1442375B1 (de)
DE (1) DE60217157T2 (de)
HK (1) HK1070147A1 (de)
WO (1) WO2003048946A2 (de)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7487339B2 (en) * 2001-10-12 2009-02-03 Mips Technologies, Inc. Method and apparatus for binding shadow registers to vectored interrupts
US20030135720A1 (en) * 2002-01-14 2003-07-17 International Business Machines Corporation Method and system using hardware assistance for instruction tracing with secondary set of interruption resources
US7065631B2 (en) * 2002-04-09 2006-06-20 Sun Microsystems, Inc. Software controllable register map
WO2004046916A2 (en) * 2002-11-18 2004-06-03 Arm Limited Exception types within a secure processing system
US7594089B2 (en) * 2003-08-28 2009-09-22 Mips Technologies, Inc. Smart memory based synchronization controller for a multi-threaded multiprocessor SoC
US7836450B2 (en) 2003-08-28 2010-11-16 Mips Technologies, Inc. Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
US7711931B2 (en) * 2003-08-28 2010-05-04 Mips Technologies, Inc. Synchronized storage providing multiple synchronization semantics
US7870553B2 (en) * 2003-08-28 2011-01-11 Mips Technologies, Inc. Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
US7418585B2 (en) * 2003-08-28 2008-08-26 Mips Technologies, Inc. Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
US7849297B2 (en) 2003-08-28 2010-12-07 Mips Technologies, Inc. Software emulation of directed exceptions in a multithreading processor
US20050050305A1 (en) * 2003-08-28 2005-03-03 Kissell Kevin D. Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
US9032404B2 (en) * 2003-08-28 2015-05-12 Mips Technologies, Inc. Preemptive multitasking employing software emulation of directed exceptions in a multithreading processor
DE602004017879D1 (de) 2003-08-28 2009-01-02 Mips Tech Inc Integrierter mechanismus zum suspendieren und endznem prozessor
US7376954B2 (en) * 2003-08-28 2008-05-20 Mips Technologies, Inc. Mechanisms for assuring quality of service for programs executing on a multithreaded processor
JP2006039874A (ja) * 2004-07-26 2006-02-09 Fujitsu Ltd 情報処理装置
JP4148223B2 (ja) * 2005-01-28 2008-09-10 セイコーエプソン株式会社 プロセッサおよび情報処理方法
US8312452B2 (en) * 2005-06-30 2012-11-13 Intel Corporation Method and apparatus for a guest to access a privileged register
KR100663709B1 (ko) * 2005-12-28 2007-01-03 삼성전자주식회사 재구성 아키텍처에서의 예외 처리 방법 및 장치
US7627705B2 (en) * 2005-12-30 2009-12-01 Stmicroelectronics Pvt. Ltd. Method and apparatus for handling interrupts in embedded systems
KR100812346B1 (ko) * 2006-02-06 2008-03-11 삼성전자주식회사 재구성 어레이에서의 인터럽트 처리 방법 및 장치
US7415557B2 (en) * 2006-06-06 2008-08-19 Honeywell International Inc. Methods and system for providing low latency and scalable interrupt collection
US10073797B2 (en) * 2008-02-22 2018-09-11 Nxp Usa, Inc. Data processor device supporting selectable exceptions and method thereof
US8417924B2 (en) * 2008-02-22 2013-04-09 Freescale Semiconductor, Inc. Data processing device and method of halting exception processing
CN101788901B (zh) * 2009-01-24 2013-09-25 世意法(北京)半导体研发有限责任公司 使用影子寄存器的高效硬件实现的设备及其方法
US8825926B2 (en) * 2009-04-13 2014-09-02 Microchip Technology Incorporated Processor with assignable general purpose register set
US8135894B1 (en) * 2009-07-31 2012-03-13 Altera Corporation Methods and systems for reducing interrupt latency by using a dedicated bit
US8392640B2 (en) * 2009-12-03 2013-03-05 Advanced Micro Devices, Inc. Pre-memory resource contention resolution
US8392644B2 (en) * 2010-07-30 2013-03-05 Mips Technologies, Inc. System and method for automatic hardware interrupt handling
CN103294544B (zh) * 2012-02-27 2016-08-17 展讯通信(上海)有限公司 嵌入式系统及其中断处理方法与装置
GB2549774B (en) 2016-04-28 2019-04-10 Imagination Tech Ltd Method for handling exceptions in exception-driven system
CN111080009B (zh) * 2019-12-13 2021-04-16 北京瑞莱智慧科技有限公司 基于时间序列的数据预测及补全方法、装置、介质和设备

Family Cites Families (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1059639A (en) * 1975-03-26 1979-07-31 Garvin W. Patterson Instruction look ahead having prefetch concurrency and pipe line features
US4056847A (en) * 1976-08-04 1977-11-01 Rca Corporation Priority vector interrupt system
US4218739A (en) 1976-10-28 1980-08-19 Honeywell Information Systems Inc. Data processing interrupt apparatus having selective suppression control
US4217638A (en) * 1977-05-19 1980-08-12 Tokyo Shibaura Electric Co., Ltd. Data-processing apparatus and method
US4296470A (en) * 1979-06-21 1981-10-20 International Business Machines Corp. Link register storage and restore system for use in an instruction pre-fetch micro-processor interrupt system
US4402042A (en) * 1980-11-24 1983-08-30 Texas Instruments Incorporated Microprocessor system with instruction pre-fetch
US4626985A (en) 1982-12-30 1986-12-02 Thomson Components - Mostek Corporation Single-chip microcomputer with internal time-multiplexed address/data/interrupt bus
NL193475C (nl) 1984-12-27 1999-11-02 Sony Corp Microprocessorinrichting.
US4826985A (en) * 1986-04-25 1989-05-02 Abbott Laboratories Intermediates for preparation of racemate and optically active ofloxacin and related derivatives
US5148544A (en) * 1987-07-01 1992-09-15 Digital Equipment Corporation Apparatus and method for control of asynchronous program interrupt events in a data processing system
JPH0795277B2 (ja) * 1988-11-25 1995-10-11 日本電気株式会社 データ処理装置
US5115506A (en) * 1990-01-05 1992-05-19 Motorola, Inc. Method and apparatus for preventing recursion jeopardy
KR960001273B1 (ko) * 1991-04-30 1996-01-25 가부시키가이샤 도시바 단일칩 마이크로컴퓨터
US5493687A (en) * 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
FR2680591B1 (fr) * 1991-08-22 1996-01-26 Telemecanique Controleur d'interruption programmable, systeme interruptif et procede de controle d'interruption.
US5404535A (en) * 1991-10-22 1995-04-04 Bull Hn Information Systems Inc. Apparatus and method for providing more effective reiterations of processing task requests in a multiprocessor system
US5371872A (en) * 1991-10-28 1994-12-06 International Business Machines Corporation Method and apparatus for controlling operation of a cache memory during an interrupt
US5386563A (en) * 1992-10-13 1995-01-31 Advanced Risc Machines Limited Register substitution during exception processing
US5868500A (en) * 1992-11-05 1999-02-09 Imi Marston Limited Slide bearing
JP2883784B2 (ja) * 1993-04-27 1999-04-19 株式会社東芝 マイクロコンピュータ
US5681255A (en) * 1993-05-21 1997-10-28 Ranpak Corp. Dispensing table and guide system for a cushioning conversion machine
US5481725A (en) 1993-08-03 1996-01-02 Intel Corporation Method for providing programmable interrupts for embedded hardware used with programmable interrupt controllers
JPH07114498A (ja) * 1993-10-15 1995-05-02 Toshiba Corp マイクロプロセッサ
DE69518145T2 (de) * 1994-02-10 2001-03-22 Elonex Technologies Inc Verzeichnis für ein-/ausgangsdecoder
WO1995032466A1 (en) * 1994-05-19 1995-11-30 Vlsi Technology, Inc. Flexible register mapping scheme
EP0689141A3 (de) 1994-06-20 1997-10-15 At & T Corp Unterbrechungsbasierte hardwaremässige Unterstützung für Systemleistungsprofilierung
US5481719A (en) * 1994-09-09 1996-01-02 International Business Machines Corporation Exception handling method and apparatus for a microkernel data processing system
WO1996012228A1 (en) * 1994-10-14 1996-04-25 Silicon Graphics, Inc. Redundant mapping tables
US5594905A (en) 1995-04-12 1997-01-14 Microsoft Corporation Exception handler and method for handling interrupts
US6148321A (en) 1995-05-05 2000-11-14 Intel Corporation Processor event recognition
US5701493A (en) * 1995-08-03 1997-12-23 Advanced Risc Machines Limited Exception handling method and apparatus in data processing systems
US5758096A (en) * 1995-08-09 1998-05-26 Barsky; Howard System and method for personalized medication treatment management
US5822595A (en) * 1995-12-29 1998-10-13 Intel Corporation Method and apparatus for providing an interrupt handler employing a token window scheme
US6094730A (en) * 1997-10-27 2000-07-25 Hewlett-Packard Company Hardware-assisted firmware tracing method and apparatus
US6178482B1 (en) * 1997-11-03 2001-01-23 Brecis Communications Virtual register sets
US5940587A (en) * 1997-12-12 1999-08-17 Intel Corporation System and method for trap address mapping for fault isolation
US6332181B1 (en) * 1998-05-04 2001-12-18 International Business Machines Corporation Recovery mechanism for L1 data cache parity errors
US6081867A (en) * 1998-05-20 2000-06-27 Sony Corporation Software configurable technique for prioritizing interrupts in a microprocessor-based system
US6243804B1 (en) * 1998-07-22 2001-06-05 Scenix Semiconductor, Inc. Single cycle transition pipeline processing using shadow registers
US6154832A (en) * 1998-12-04 2000-11-28 Advanced Micro Devices, Inc. Processor employing multiple register sets to eliminate interrupts
US6477562B2 (en) * 1998-12-16 2002-11-05 Clearwater Networks, Inc. Prioritized instruction scheduling for multi-streaming processors
US7020879B1 (en) 1998-12-16 2006-03-28 Mips Technologies, Inc. Interrupt and exception handling for multi-streaming digital processors
GB9909626D0 (en) 1999-04-27 1999-06-23 Hewlett Packard Ltd Loop prevention in networks
US6499078B1 (en) 1999-07-19 2002-12-24 Microsoft Corporation Interrupt handler with prioritized interrupt vector generator
US6574693B1 (en) * 1999-10-11 2003-06-03 Ati International Srl Method and apparatus for gating interrupts in a computing system
US6651126B1 (en) * 1999-10-29 2003-11-18 Texas Instruments Incorporated Snapshot arbiter mechanism
US7165257B2 (en) 2000-02-08 2007-01-16 Mips Technologies, Inc. Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts
US6539448B1 (en) * 2000-05-26 2003-03-25 Texas Instruments Incorporated Priority first come first serve interrupt controller
US6822959B2 (en) 2000-07-31 2004-11-23 Mindspeed Technologies, Inc. Enhancing performance by pre-fetching and caching data directly in a communication processor's register set
US6889279B2 (en) * 2000-12-11 2005-05-03 Cadence Design Systems, Inc. Pre-stored vector interrupt handling system and method
US6470435B2 (en) * 2000-12-28 2002-10-22 Intel Corporation Dual state rename recovery using register usage
KR20030004763A (ko) 2001-07-06 2003-01-15 삼성전자 주식회사 인터럽트 처리장치
US7487339B2 (en) 2001-10-12 2009-02-03 Mips Technologies, Inc. Method and apparatus for binding shadow registers to vectored interrupts
US7552261B2 (en) * 2001-10-12 2009-06-23 Mips Technologies, Inc. Configurable prioritization of core generated interrupts
US20030088723A1 (en) 2001-11-08 2003-05-08 Mackey Richard P. System and method for processing interrupts

Also Published As

Publication number Publication date
EP1442375A2 (de) 2004-08-04
US20090119434A1 (en) 2009-05-07
EP1442375B1 (de) 2006-12-27
DE60217157T2 (de) 2007-10-04
US7925864B2 (en) 2011-04-12
WO2003048946A3 (en) 2004-01-22
WO2003048946A2 (en) 2003-06-12
US7487339B2 (en) 2009-02-03
US20060253635A1 (en) 2006-11-09
US7487332B2 (en) 2009-02-03
HK1070147A1 (en) 2005-06-10
EP1772807A1 (de) 2007-04-11
US20030074545A1 (en) 2003-04-17
US20070124569A1 (en) 2007-05-31
US8181000B2 (en) 2012-05-15

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