DE60222219D1 - Interne Cache-Speicherblockausräumung mit externer Anforderung - Google Patents
Interne Cache-Speicherblockausräumung mit externer AnforderungInfo
- Publication number
- DE60222219D1 DE60222219D1 DE60222219T DE60222219T DE60222219D1 DE 60222219 D1 DE60222219 D1 DE 60222219D1 DE 60222219 T DE60222219 T DE 60222219T DE 60222219 T DE60222219 T DE 60222219T DE 60222219 D1 DE60222219 D1 DE 60222219D1
- Authority
- DE
- Germany
- Prior art keywords
- cache block
- internal cache
- external request
- block flush
- flush
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
- G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US909009 | 1992-07-06 | ||
US09/909,009 US6697918B2 (en) | 2001-07-18 | 2001-07-18 | Cache configured to read evicted cache block responsive to transmitting block's address on interface |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60222219D1 true DE60222219D1 (de) | 2007-10-18 |
DE60222219T2 DE60222219T2 (de) | 2008-05-29 |
Family
ID=25426503
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60222219T Expired - Lifetime DE60222219T2 (de) | 2001-07-18 | 2002-07-17 | Interne Cache-Speicherblockausräumung mit externer Anforderung |
Country Status (3)
Country | Link |
---|---|
US (3) | US6697918B2 (de) |
EP (1) | EP1284457B1 (de) |
DE (1) | DE60222219T2 (de) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8391039B2 (en) * | 2001-04-24 | 2013-03-05 | Rambus Inc. | Memory module with termination component |
US6675272B2 (en) | 2001-04-24 | 2004-01-06 | Rambus Inc. | Method and apparatus for coordinating memory operations among diversely-located memory components |
US7027064B2 (en) * | 2002-02-28 | 2006-04-11 | Sun Microsystems, Inc. | Active block write-back from SRAM cache to DRAM |
DE60336461D1 (de) * | 2002-04-30 | 2011-05-05 | Dsp Group Switzerland Ag | Lüchtigen speicher in einer integrierten schaltung und integrierte schaltung hierfür |
US7346757B2 (en) * | 2002-10-08 | 2008-03-18 | Rmi Corporation | Advanced processor translation lookaside buffer management in a multithreaded system |
US8176298B2 (en) * | 2002-10-08 | 2012-05-08 | Netlogic Microsystems, Inc. | Multi-core multi-threaded processing systems with instruction reordering in an in-order pipeline |
US8478811B2 (en) * | 2002-10-08 | 2013-07-02 | Netlogic Microsystems, Inc. | Advanced processor with credit based scheme for optimal packet flow in a multi-processor system on a chip |
US7627721B2 (en) * | 2002-10-08 | 2009-12-01 | Rmi Corporation | Advanced processor with cache coherency |
US7461213B2 (en) * | 2002-10-08 | 2008-12-02 | Rmi Corporation | Advanced processor system using request, data, snoop, and response rings |
US8015567B2 (en) | 2002-10-08 | 2011-09-06 | Netlogic Microsystems, Inc. | Advanced processor with mechanism for packet distribution at high line rate |
US20050033889A1 (en) * | 2002-10-08 | 2005-02-10 | Hass David T. | Advanced processor with interrupt delivery mechanism for multi-threaded multi-CPU system on a chip |
US7984268B2 (en) * | 2002-10-08 | 2011-07-19 | Netlogic Microsystems, Inc. | Advanced processor scheduling in a multithreaded system |
US8037224B2 (en) | 2002-10-08 | 2011-10-11 | Netlogic Microsystems, Inc. | Delegating network processor operations to star topology serial bus interfaces |
US9088474B2 (en) * | 2002-10-08 | 2015-07-21 | Broadcom Corporation | Advanced processor with interfacing messaging network to a CPU |
US7924828B2 (en) * | 2002-10-08 | 2011-04-12 | Netlogic Microsystems, Inc. | Advanced processor with mechanism for fast packet queuing operations |
US7334086B2 (en) | 2002-10-08 | 2008-02-19 | Rmi Corporation | Advanced processor with system on a chip interconnect technology |
US7961723B2 (en) * | 2002-10-08 | 2011-06-14 | Netlogic Microsystems, Inc. | Advanced processor with mechanism for enforcing ordering between information sent on two independent networks |
US7464227B2 (en) * | 2002-12-10 | 2008-12-09 | Intel Corporation | Method and apparatus for supporting opportunistic sharing in coherent multiprocessors |
US7301831B2 (en) | 2004-09-15 | 2007-11-27 | Rambus Inc. | Memory systems with variable delays for write data signals |
US7330941B2 (en) * | 2005-03-23 | 2008-02-12 | Qualcomm Incorporated | Global modified indicator to reduce power consumption on cache miss |
JP4038216B2 (ja) * | 2005-05-10 | 2008-01-23 | ファナック株式会社 | シーケンスプログラム編集装置 |
US20080307169A1 (en) * | 2007-06-06 | 2008-12-11 | Duane Arlyn Averill | Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory |
US8296534B1 (en) * | 2007-06-29 | 2012-10-23 | Emc Corporation | Techniques for using flash-based memory in recovery processing |
US9596324B2 (en) * | 2008-02-08 | 2017-03-14 | Broadcom Corporation | System and method for parsing and allocating a plurality of packets to processor core threads |
KR101378602B1 (ko) * | 2008-05-13 | 2014-03-25 | 삼성전자주식회사 | 메모리 장치 및 메모리 프로그래밍 방법 |
US9317423B2 (en) * | 2013-01-07 | 2016-04-19 | Hitachi, Ltd. | Storage system which realizes asynchronous remote copy using cache memory composed of flash memory, and control method thereof |
US20190065373A1 (en) * | 2017-08-30 | 2019-02-28 | Micron Technology, Inc. | Cache buffer |
US11803470B2 (en) * | 2020-09-25 | 2023-10-31 | Advanced Micro Devices, Inc. | Multi-level cache coherency protocol for cache line evictions |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5809524A (en) * | 1994-01-04 | 1998-09-15 | Intel Corporation | Method and apparatus for cache memory replacement line identification |
US5526510A (en) * | 1994-02-28 | 1996-06-11 | Intel Corporation | Method and apparatus for implementing a single clock cycle line replacement in a data cache unit |
US6047357A (en) * | 1995-01-27 | 2000-04-04 | Digital Equipment Corporation | High speed method for maintaining cache coherency in a multi-level, set associative cache hierarchy |
US5860117A (en) * | 1996-05-31 | 1999-01-12 | Sun Microsystems, Inc. | Apparatus and method to improve primary memory latencies using an eviction buffer to store write requests |
US6038645A (en) | 1996-08-28 | 2000-03-14 | Texas Instruments Incorporated | Microprocessor circuits, systems, and methods using a combined writeback queue and victim cache |
US5883826A (en) * | 1996-09-30 | 1999-03-16 | Wendell; Dennis Lee | Memory block select using multiple word lines to address a single memory cell row |
US6105108A (en) * | 1997-10-24 | 2000-08-15 | Compaq Computer Corporation | Method and apparatus for releasing victim data buffers of computer systems by comparing a probe counter with a service counter |
US6202126B1 (en) * | 1997-10-24 | 2001-03-13 | Compaq Computer Corporation | Victimization of clean data blocks |
US6240487B1 (en) * | 1998-02-18 | 2001-05-29 | International Business Machines Corporation | Integrated cache buffers |
US6393529B1 (en) * | 1998-12-21 | 2002-05-21 | Advanced Micro Devices, Inc. | Conversation of distributed memory bandwidth in multiprocessor system with cache coherency by transmitting cancel subsequent to victim write |
US6519685B1 (en) * | 1999-12-22 | 2003-02-11 | Intel Corporation | Cache states for multiprocessor cache coherency protocols |
US6751720B2 (en) * | 2000-06-10 | 2004-06-15 | Hewlett-Packard Development Company, L.P. | Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy |
US6745297B2 (en) * | 2000-10-06 | 2004-06-01 | Broadcom Corporation | Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent |
US6499085B2 (en) * | 2000-12-29 | 2002-12-24 | Intel Corporation | Method and system for servicing cache line in response to partial cache line request |
-
2001
- 2001-07-18 US US09/909,009 patent/US6697918B2/en not_active Expired - Lifetime
-
2002
- 2002-07-17 DE DE60222219T patent/DE60222219T2/de not_active Expired - Lifetime
- 2002-07-17 EP EP02015677A patent/EP1284457B1/de not_active Expired - Fee Related
-
2003
- 2003-12-30 US US10/748,564 patent/US6918008B2/en not_active Expired - Fee Related
-
2005
- 2005-06-07 US US11/146,563 patent/US20050228953A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20030018856A1 (en) | 2003-01-23 |
EP1284457A2 (de) | 2003-02-19 |
DE60222219T2 (de) | 2008-05-29 |
EP1284457B1 (de) | 2007-09-05 |
EP1284457A3 (de) | 2004-03-17 |
US20050228953A1 (en) | 2005-10-13 |
US6918008B2 (en) | 2005-07-12 |
US6697918B2 (en) | 2004-02-24 |
US20040153482A1 (en) | 2004-08-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Representative=s name: BOSCH JEHLE PATENTANWALTSGESELLSCHAFT MBH, 80639 M |