DE60222947D1 - Halbleiterspeicher - Google Patents

Halbleiterspeicher

Info

Publication number
DE60222947D1
DE60222947D1 DE60222947T DE60222947T DE60222947D1 DE 60222947 D1 DE60222947 D1 DE 60222947D1 DE 60222947 T DE60222947 T DE 60222947T DE 60222947 T DE60222947 T DE 60222947T DE 60222947 D1 DE60222947 D1 DE 60222947D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60222947T
Other languages
English (en)
Other versions
DE60222947T2 (de
Inventor
Shinya Fujioka
Yoshiaki Okuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE60222947D1 publication Critical patent/DE60222947D1/de
Application granted granted Critical
Publication of DE60222947T2 publication Critical patent/DE60222947T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
DE60222947T 2002-04-15 2002-11-18 Halbleiterspeicher Expired - Lifetime DE60222947T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2002111877 2002-04-15
JP2002111877 2002-04-15
JP2002156832A JP4078119B2 (ja) 2002-04-15 2002-05-30 半導体メモリ
JP2002156832 2002-05-30

Publications (2)

Publication Number Publication Date
DE60222947D1 true DE60222947D1 (de) 2007-11-22
DE60222947T2 DE60222947T2 (de) 2008-02-14

Family

ID=28677636

Family Applications (2)

Application Number Title Priority Date Filing Date
DE60222947T Expired - Lifetime DE60222947T2 (de) 2002-04-15 2002-11-18 Halbleiterspeicher
DE60213560T Expired - Lifetime DE60213560T2 (de) 2002-04-15 2002-11-18 Halbleiterspeicher

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE60213560T Expired - Lifetime DE60213560T2 (de) 2002-04-15 2002-11-18 Halbleiterspeicher

Country Status (7)

Country Link
US (2) US6847570B2 (de)
EP (2) EP1355318B1 (de)
JP (1) JP4078119B2 (de)
KR (2) KR100888833B1 (de)
CN (1) CN1225697C (de)
DE (2) DE60222947T2 (de)
TW (1) TW580704B (de)

Families Citing this family (48)

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JP2003297080A (ja) * 2002-03-29 2003-10-17 Mitsubishi Electric Corp 半導体記憶装置
KR100481818B1 (ko) * 2002-07-24 2005-04-11 (주)실리콘세븐 디램 셀을 사용하며, 버스트 억세스 구동이 가능한 동기식 에스램 호환 메모리 및 그 구동 방법
JP2005085289A (ja) * 2003-09-04 2005-03-31 Elpida Memory Inc 半導体記憶装置
JP4996094B2 (ja) * 2003-10-24 2012-08-08 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体記憶装置及びそのリフレッシュ方法
JP2005285271A (ja) * 2004-03-30 2005-10-13 Nec Electronics Corp 半導体記憶装置
JP4717373B2 (ja) * 2004-05-20 2011-07-06 富士通セミコンダクター株式会社 半導体メモリ
JP4615896B2 (ja) * 2004-05-25 2011-01-19 富士通セミコンダクター株式会社 半導体記憶装置および該半導体記憶装置の制御方法
EP1770711B1 (de) * 2004-07-16 2008-12-31 Fujitsu Ltd. Halbleiter-speicherbaustein
JP4275033B2 (ja) * 2004-08-23 2009-06-10 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置とテスト回路及び方法
JP4562468B2 (ja) * 2004-09-13 2010-10-13 ルネサスエレクトロニクス株式会社 半導体記憶装置
KR100564633B1 (ko) 2004-09-25 2006-03-28 삼성전자주식회사 향상된 동작 성능을 가지는 반도체 메모리 장치 및 이에대한 액세스 제어 방법
KR100549871B1 (ko) * 2004-10-22 2006-02-06 삼성전자주식회사 데이터 핀의 상태에 의해서 동작 모드가 결정되는 반도체메모리 장치 및 이를 이용한 동작 모드 결정 방법
JP4329697B2 (ja) 2005-01-12 2009-09-09 ヤマハ株式会社 音楽再生装置および同装置に適用されるコンピュータ読み取り可能な音楽再生プログラム
KR100600331B1 (ko) * 2005-05-30 2006-07-18 주식회사 하이닉스반도체 연속적인 버스트 모드로 동작 가능한 슈도 ｓｒａｍ
JP4753637B2 (ja) * 2005-06-23 2011-08-24 パトレネラ キャピタル リミテッド， エルエルシー メモリ
KR100670665B1 (ko) * 2005-06-30 2007-01-17 주식회사 하이닉스반도체 반도체 메모리 장치의 레이턴시 제어 회로
KR100695512B1 (ko) 2005-06-30 2007-03-15 주식회사 하이닉스반도체 반도체 메모리 장치
JP4362573B2 (ja) * 2005-07-28 2009-11-11 パトレネラ キャピタル リミテッド， エルエルシー メモリ
JP4518563B2 (ja) * 2005-09-02 2010-08-04 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体記憶装置
JP4234126B2 (ja) 2005-09-28 2009-03-04 インターナショナル・ビジネス・マシーンズ・コーポレーション メモリ、メモリ・アクセス制御方法
JP2007115087A (ja) * 2005-10-21 2007-05-10 Oki Electric Ind Co Ltd 半導体装置
KR100646271B1 (ko) * 2005-12-08 2006-11-23 주식회사 하이닉스반도체 반도체 메모리 장치
KR100689863B1 (ko) 2005-12-22 2007-03-08 삼성전자주식회사 반도체 메모리 장치 및 그에 따른 방법
JP2007250087A (ja) * 2006-03-16 2007-09-27 Fujitsu Ltd ダイナミックメモリコントローラ
JP2007273028A (ja) * 2006-03-31 2007-10-18 Matsushita Electric Ind Co Ltd 半導体記憶装置
JP5011818B2 (ja) 2006-05-19 2012-08-29 富士通セミコンダクター株式会社 半導体記憶装置及びその試験方法
CN100547575C (zh) * 2006-09-12 2009-10-07 威盛电子股份有限公司 初始设定装置的方法及初始设定系统
KR100837811B1 (ko) * 2006-11-15 2008-06-13 주식회사 하이닉스반도체 데이터 변환 회로 및 이를 이용한 반도체 메모리 장치
JP5228472B2 (ja) * 2007-12-19 2013-07-03 富士通セミコンダクター株式会社 半導体メモリおよびシステム
KR100929836B1 (ko) * 2008-06-04 2009-12-07 주식회사 하이닉스반도체 반도체 소자
JP5256879B2 (ja) * 2008-06-23 2013-08-07 富士通セミコンダクター株式会社 半導体記憶装置
US7894290B2 (en) * 2008-10-22 2011-02-22 Qimonda Ag Method and apparatus for performing internal hidden refreshes while latching read/write commands, address and data information for later operation
US7859932B2 (en) * 2008-12-18 2010-12-28 Sandisk Corporation Data refresh for non-volatile storage
TWI401694B (zh) * 2009-01-14 2013-07-11 Nanya Technology Corp 動態隨機存取記憶體行命令位址的控制電路及方法
KR200458368Y1 (ko) * 2009-03-25 2012-02-15 최구락 창틀고정용 환기장치
KR20110001396A (ko) * 2009-06-30 2011-01-06 삼성전자주식회사 전력 소모를 줄일 수 있는 반도체 메모리 장치
KR101060899B1 (ko) * 2009-12-23 2011-08-30 주식회사 하이닉스반도체 반도체 메모리 장치 및 이의 동작 방법
KR101096222B1 (ko) * 2009-12-30 2011-12-22 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 동작 방법
JP5430484B2 (ja) 2010-04-15 2014-02-26 ルネサスエレクトロニクス株式会社 半導体記憶装置、及びその制御方法
US8854873B1 (en) * 2011-05-05 2014-10-07 Adesto Technologies Corporation Memory devices, architectures and methods for memory elements having dynamic change in property
JP2013229068A (ja) * 2012-04-24 2013-11-07 Ps4 Luxco S A R L 半導体装置及びこれを備える情報処理システム
JP5429335B2 (ja) * 2012-08-15 2014-02-26 富士通セミコンダクター株式会社 半導体メモリおよびシステム
US9311977B2 (en) * 2014-08-27 2016-04-12 Stmicroelectronics Asia Pacific Pte Ltd Event controlled decoding circuit
KR102370156B1 (ko) * 2017-08-23 2022-03-07 삼성전자주식회사 메모리 시스템, 및 이를 위한 메모리 모듈과 반도체 메모리 장치
JP6429260B1 (ja) * 2017-11-09 2018-11-28 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． 疑似スタティックランダムアクセスメモリおよびそのリフレッシュ方法
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KR20210158571A (ko) * 2020-06-24 2021-12-31 에스케이하이닉스 주식회사 레이턴시 설정 회로를 포함하는 반도체 메모리 장치

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Also Published As

Publication number Publication date
TW200305161A (en) 2003-10-16
EP1355318B1 (de) 2006-08-02
EP1355318A2 (de) 2003-10-22
US20030198098A1 (en) 2003-10-23
CN1225697C (zh) 2005-11-02
KR20080075467A (ko) 2008-08-18
EP1355318A3 (de) 2004-09-29
CN1452177A (zh) 2003-10-29
EP1612803A1 (de) 2006-01-04
JP4078119B2 (ja) 2008-04-23
KR100895661B1 (ko) 2009-05-07
DE60222947T2 (de) 2008-02-14
EP1612803B1 (de) 2007-10-10
DE60213560D1 (de) 2006-09-14
JP2004005780A (ja) 2004-01-08
US20050073903A1 (en) 2005-04-07
TW580704B (en) 2004-03-21
KR20030082353A (ko) 2003-10-22
DE60213560T2 (de) 2007-10-25
US6847570B2 (en) 2005-01-25
US7050353B2 (en) 2006-05-23
KR100888833B1 (ko) 2009-03-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE