DE60227985D1 - Programmierbares gatterfeld mit verbindungslogik zur unterstützung von eingebetteten festlogikschaltungen - Google Patents

Programmierbares gatterfeld mit verbindungslogik zur unterstützung von eingebetteten festlogikschaltungen

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Publication number
DE60227985D1
DE60227985D1 DE60227985T DE60227985T DE60227985D1 DE 60227985 D1 DE60227985 D1 DE 60227985D1 DE 60227985 T DE60227985 T DE 60227985T DE 60227985 T DE60227985 T DE 60227985T DE 60227985 D1 DE60227985 D1 DE 60227985D1
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DE
Germany
Prior art keywords
programmable gate
logic
gate board
link
support embedded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60227985T
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English (en)
Inventor
Stephen M Douglass
Steven P Young
Nigel G Herron
Mehul R Vashi
Jane W Sowards
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Xilinx Inc
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Xilinx Inc
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Publication of DE60227985D1 publication Critical patent/DE60227985D1/de
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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management
DE60227985T 2001-09-28 2002-09-23 Programmierbares gatterfeld mit verbindungslogik zur unterstützung von eingebetteten festlogikschaltungen Expired - Lifetime DE60227985D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/968,446 US6798239B2 (en) 2001-09-28 2001-09-28 Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
PCT/US2002/030240 WO2003030009A2 (en) 2001-09-28 2002-09-23 Programmable gate array having interconnecting logic to support embedded fixed logic circuitry

Publications (1)

Publication Number Publication Date
DE60227985D1 true DE60227985D1 (de) 2008-09-11

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DE60227985T Expired - Lifetime DE60227985D1 (de) 2001-09-28 2002-09-23 Programmierbares gatterfeld mit verbindungslogik zur unterstützung von eingebetteten festlogikschaltungen

Country Status (6)

Country Link
US (1) US6798239B2 (de)
EP (1) EP1454257B1 (de)
JP (1) JP3939698B2 (de)
CA (1) CA2458060C (de)
DE (1) DE60227985D1 (de)
WO (1) WO2003030009A2 (de)

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US6798239B2 (en) 2004-09-28
EP1454257B1 (de) 2008-07-30
CA2458060A1 (en) 2003-04-10
EP1454257A2 (de) 2004-09-08
US20030062922A1 (en) 2003-04-03
JP3939698B2 (ja) 2007-07-04
WO2003030009A2 (en) 2003-04-10
CA2458060C (en) 2009-09-22
JP2005512359A (ja) 2005-04-28
WO2003030009A3 (en) 2004-06-17

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