DE60301915D1 - System und Verfahren zur Konfiguration analoger Elemente eines konfigurierbaren Gerätes - Google Patents

System und Verfahren zur Konfiguration analoger Elemente eines konfigurierbaren Gerätes

Info

Publication number
DE60301915D1
DE60301915D1 DE60301915T DE60301915T DE60301915D1 DE 60301915 D1 DE60301915 D1 DE 60301915D1 DE 60301915 T DE60301915 T DE 60301915T DE 60301915 T DE60301915 T DE 60301915T DE 60301915 D1 DE60301915 D1 DE 60301915D1
Authority
DE
Germany
Prior art keywords
programmable
configurable hardware
memory locations
hardware device
configuration data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60301915T
Other languages
English (en)
Inventor
Danny Austin Bersch
Ian Craig Macbeth
Howard Charles Anderson
Brian Eugene Nottingham
Troy Franklin Giles
Timothy James Streit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anadigm Inc
Original Assignee
Anadigm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anadigm Inc filed Critical Anadigm Inc
Application granted granted Critical
Publication of DE60301915D1 publication Critical patent/DE60301915D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/34Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/343Logical level
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/34Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/36Circuit design at the analogue level
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/38Circuit design at the mixed level of analogue and digital signals
DE60301915T 2002-06-11 2003-06-11 System und Verfahren zur Konfiguration analoger Elemente eines konfigurierbaren Gerätes Expired - Lifetime DE60301915D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/171,334 US7024654B2 (en) 2002-06-11 2002-06-11 System and method for configuring analog elements in a configurable hardware device

Publications (1)

Publication Number Publication Date
DE60301915D1 true DE60301915D1 (de) 2005-11-24

Family

ID=29711063

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60301915T Expired - Lifetime DE60301915D1 (de) 2002-06-11 2003-06-11 System und Verfahren zur Konfiguration analoger Elemente eines konfigurierbaren Gerätes

Country Status (5)

Country Link
US (1) US7024654B2 (de)
EP (1) EP1376416B1 (de)
JP (1) JP2004110771A (de)
AT (1) ATE307360T1 (de)
DE (1) DE60301915D1 (de)

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Also Published As

Publication number Publication date
US20030229877A1 (en) 2003-12-11
ATE307360T1 (de) 2005-11-15
US7024654B2 (en) 2006-04-04
JP2004110771A (ja) 2004-04-08
EP1376416A1 (de) 2004-01-02
EP1376416B1 (de) 2005-10-19

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