DE60309422D1 - Multichip-modul und Herstellungsverfahren - Google Patents

Multichip-modul und Herstellungsverfahren

Info

Publication number
DE60309422D1
DE60309422D1 DE60309422T DE60309422T DE60309422D1 DE 60309422 D1 DE60309422 D1 DE 60309422D1 DE 60309422 T DE60309422 T DE 60309422T DE 60309422 T DE60309422 T DE 60309422T DE 60309422 D1 DE60309422 D1 DE 60309422D1
Authority
DE
Germany
Prior art keywords
manufacturing process
chip module
chip
module
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60309422T
Other languages
English (en)
Other versions
DE60309422T2 (de
Inventor
Scott D Brandenburg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Delphi Technologies Inc
Original Assignee
Delphi Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Delphi Technologies Inc filed Critical Delphi Technologies Inc
Application granted granted Critical
Publication of DE60309422D1 publication Critical patent/DE60309422D1/de
Publication of DE60309422T2 publication Critical patent/DE60309422T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385Assembly of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00015Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
DE60309422T 2002-12-17 2003-11-28 Multichip-modul und Herstellungsverfahren Expired - Fee Related DE60309422T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US321900 2002-12-17
US10/321,900 US6833628B2 (en) 2002-12-17 2002-12-17 Mutli-chip module

Publications (2)

Publication Number Publication Date
DE60309422D1 true DE60309422D1 (de) 2006-12-14
DE60309422T2 DE60309422T2 (de) 2007-10-11

Family

ID=32393007

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60309422T Expired - Fee Related DE60309422T2 (de) 2002-12-17 2003-11-28 Multichip-modul und Herstellungsverfahren

Country Status (3)

Country Link
US (2) US6833628B2 (de)
EP (1) EP1432033B1 (de)
DE (1) DE60309422T2 (de)

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TW569416B (en) * 2002-12-19 2004-01-01 Via Tech Inc High density multi-chip module structure and manufacturing method thereof
US6916684B2 (en) * 2003-03-18 2005-07-12 Delphi Technologies, Inc. Wafer-applied underfill process
DE10323007B4 (de) 2003-05-21 2005-10-20 Infineon Technologies Ag Halbleiteranordnung
US20050017337A1 (en) * 2003-07-21 2005-01-27 Cherng-Chiao Wu Stacking apparatus for integrated circuit assembly
KR101075169B1 (ko) * 2003-08-27 2011-10-19 페어차일드코리아반도체 주식회사 파워 모듈 플립 칩 패키지
JP2005158814A (ja) * 2003-11-20 2005-06-16 Alps Electric Co Ltd 電子回路ユニット
WO2005067029A1 (en) * 2004-01-06 2005-07-21 Infineon Technologies Ag Method for packaging integrated circuit dies
KR100640335B1 (ko) * 2004-10-28 2006-10-30 삼성전자주식회사 랜드 그리드 어레이 모듈
US7473585B2 (en) * 2005-06-13 2009-01-06 Delphi Technologies, Inc. Technique for manufacturing an overmolded electronic assembly
US20070158811A1 (en) * 2006-01-11 2007-07-12 James Douglas Wehrly Low profile managed memory component
KR100782774B1 (ko) * 2006-05-25 2007-12-05 삼성전기주식회사 Sip 모듈
TW200807647A (en) * 2006-07-17 2008-02-01 Delta Electronics Inc Integrated circuit module
WO2008120756A1 (ja) * 2007-03-29 2008-10-09 Kyocera Corporation 携帯無線機
US8134227B2 (en) * 2007-03-30 2012-03-13 Stats Chippac Ltd. Stacked integrated circuit package system with conductive spacer
US7915089B2 (en) * 2007-04-10 2011-03-29 Infineon Technologies Ag Encapsulation method
US7973433B2 (en) * 2007-07-30 2011-07-05 Nelson David F Power electronics devices with integrated gate drive circuitry
US8139371B2 (en) * 2007-07-30 2012-03-20 GM Global Technology Operations LLC Power electronics devices with integrated control circuitry
US8273603B2 (en) * 2008-04-04 2012-09-25 The Charles Stark Draper Laboratory, Inc. Interposers, electronic modules, and methods for forming the same
US8017451B2 (en) 2008-04-04 2011-09-13 The Charles Stark Draper Laboratory, Inc. Electronic modules and methods for forming the same
US9293350B2 (en) * 2008-10-28 2016-03-22 Stats Chippac Ltd. Semiconductor package system with cavity substrate and manufacturing method therefor
US8618654B2 (en) 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
KR101088824B1 (ko) * 2010-06-16 2011-12-06 주식회사 하이닉스반도체 모듈 기판, 이를 갖는 메모리 모듈 및 메모리 모듈 형성방법
CN106935577A (zh) * 2011-03-22 2017-07-07 晶元光电股份有限公司 发光二极管装置
US8514576B1 (en) * 2011-06-14 2013-08-20 Juniper Networks, Inc. Dual sided system in a package
EP2565913B1 (de) * 2011-06-22 2019-03-20 Huawei Device Co., Ltd. Verfahren zur einkapselung eines halbleiters
US20130020702A1 (en) * 2011-07-21 2013-01-24 Jun Zhai Double-sided flip chip package
US20130082383A1 (en) * 2011-10-03 2013-04-04 Texas Instruments Incorporated Electronic assembly having mixed interface including tsv die
US8698323B2 (en) * 2012-06-18 2014-04-15 Invensas Corporation Microelectronic assembly tolerant to misplacement of microelectronic elements therein
KR20150025129A (ko) * 2013-08-28 2015-03-10 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법
US9076802B1 (en) * 2013-09-25 2015-07-07 Stats Chippac Ltd. Dual-sided film-assist molding process
CN104576411A (zh) * 2013-10-25 2015-04-29 飞思卡尔半导体公司 双角部顶部闸道模制
US9392695B2 (en) * 2014-01-03 2016-07-12 Samsung Electro-Mechanics Co., Ltd. Electric component module
US9666559B2 (en) * 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
TWI590392B (zh) * 2015-08-03 2017-07-01 矽品精密工業股份有限公司 電子封裝件及其製法
TWI676259B (zh) * 2016-09-02 2019-11-01 矽品精密工業股份有限公司 電子封裝件及其製法
KR20180090527A (ko) * 2017-02-03 2018-08-13 삼성전기주식회사 반도체 패키지와 그 제조 방법
US20220367413A1 (en) * 2021-05-13 2022-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Packages With Multiple Types of Underfill and Method Forming The Same
US11747555B2 (en) 2021-10-04 2023-09-05 Eagle Technology, Llc Optical assembly having commonly-shaped optical modules and associated methods

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JP2541487B2 (ja) 1993-11-29 1996-10-09 日本電気株式会社 半導体装置パッケ―ジ
JPH0846136A (ja) * 1994-07-26 1996-02-16 Fujitsu Ltd 半導体装置
US5608262A (en) * 1995-02-24 1997-03-04 Lucent Technologies Inc. Packaging multi-chip modules without wire-bond interconnection
US5770477A (en) 1997-02-10 1998-06-23 Delco Electronics Corporation Flip chip-on-flip chip multi-chip module
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US6383846B1 (en) * 2000-03-20 2002-05-07 Chi-Chih Shen Method and apparatus for molding a flip chip semiconductor device

Also Published As

Publication number Publication date
US6833628B2 (en) 2004-12-21
EP1432033A1 (de) 2004-06-23
DE60309422T2 (de) 2007-10-11
US20040113281A1 (en) 2004-06-17
EP1432033B1 (de) 2006-11-02
US20050093144A1 (en) 2005-05-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee