DE60310528D1 - Verfahren zur Strukturierung einer Chalkogenid-Schicht, insbesondere in einem Verfahren zur Herstellung von Phasenwechsel-Speicherzellen - Google Patents

Verfahren zur Strukturierung einer Chalkogenid-Schicht, insbesondere in einem Verfahren zur Herstellung von Phasenwechsel-Speicherzellen

Info

Publication number
DE60310528D1
DE60310528D1 DE60310528T DE60310528T DE60310528D1 DE 60310528 D1 DE60310528 D1 DE 60310528D1 DE 60310528 T DE60310528 T DE 60310528T DE 60310528 T DE60310528 T DE 60310528T DE 60310528 D1 DE60310528 D1 DE 60310528D1
Authority
DE
Germany
Prior art keywords
structuring
memory cells
phase change
change memory
chalcogenide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60310528T
Other languages
English (en)
Other versions
DE60310528T2 (de
Inventor
Alessandro Spandre
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Ovonyx Inc
Original Assignee
STMicroelectronics SRL
Ovonyx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL, Ovonyx Inc filed Critical STMicroelectronics SRL
Publication of DE60310528D1 publication Critical patent/DE60310528D1/de
Application granted granted Critical
Publication of DE60310528T2 publication Critical patent/DE60310528T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
DE60310528T 2003-05-07 2003-05-07 Verfahren zum Festlegen einer Chalcogenidmaterial-Schicht, insbesondere in einem Verfahren zur Herstellung von Phasenumwandlungs-Speicherzellen Expired - Lifetime DE60310528T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03425293A EP1475848B1 (de) 2003-05-07 2003-05-07 Verfahren zur Strukturierung einer Chalkogenid-Schicht, insbesondere in einem Verfahren zur Herstellung von Phasenwechsel-Speicherzellen

Publications (2)

Publication Number Publication Date
DE60310528D1 true DE60310528D1 (de) 2007-02-01
DE60310528T2 DE60310528T2 (de) 2007-09-27

Family

ID=32982047

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60310528T Expired - Lifetime DE60310528T2 (de) 2003-05-07 2003-05-07 Verfahren zum Festlegen einer Chalcogenidmaterial-Schicht, insbesondere in einem Verfahren zur Herstellung von Phasenumwandlungs-Speicherzellen

Country Status (3)

Country Link
US (1) US7256130B2 (de)
EP (1) EP1475848B1 (de)
DE (1) DE60310528T2 (de)

Families Citing this family (15)

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WO2005011011A1 (en) * 2003-07-21 2005-02-03 Unaxis Usa Inc. Etching method for making chalcogenide memory elements
US20060169968A1 (en) * 2005-02-01 2006-08-03 Thomas Happ Pillar phase change memory cell
US20070045606A1 (en) * 2005-08-30 2007-03-01 Michele Magistretti Shaping a phase change layer in a phase change memory cell
US20070166870A1 (en) * 2006-01-17 2007-07-19 Samsung Electronics Co., Ltd. Method of forming a phase-changeable structure
KR100889970B1 (ko) * 2006-01-20 2009-03-24 삼성전자주식회사 상변화 구조물 형성 방법
US7569430B2 (en) * 2006-02-13 2009-08-04 Samsung Electronics Co., Ltd. Phase changeable structure and method of forming the same
US7682979B2 (en) * 2006-06-29 2010-03-23 Lam Research Corporation Phase change alloy etch
US7967994B2 (en) * 2007-10-25 2011-06-28 Ovonyx, Inc. Method and apparatus for chalcogenide device formation
US7799696B2 (en) * 2007-12-20 2010-09-21 Qimonda Ag Method of manufacturing an integrated circuit
EP2232602B1 (de) * 2008-01-16 2011-10-05 Nxp B.V. Mehrschichtige struktur mit einer phasenwechselmaterialschicht und verfahren zu ihrer herstellung
KR100968888B1 (ko) * 2008-10-01 2010-07-09 한국전자통신연구원 상변화 메모리 소자를 이용한 비휘발성 프로그래머블 스위치 소자 및 그 제조 방법
US8420947B2 (en) * 2010-12-30 2013-04-16 Globalfoundries Singapore Pte. Ltd. Integrated circuit system with ultra-low k dielectric and method of manufacture thereof
US8822256B1 (en) 2013-04-04 2014-09-02 Bae Systems Information And Electronic Systems Integration Inc. Method for fabricating infrared sensors
FR3116836B1 (fr) 2020-11-27 2023-03-24 Commissariat Energie Atomique Procédé pour augmenter la rugosité de surface d’une couche métallique
CN115938937B (zh) * 2023-03-09 2023-06-09 合肥晶合集成电路股份有限公司 半导体结构及其制备方法

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JPS5565365A (en) 1978-11-07 1980-05-16 Nippon Telegr & Teleph Corp <Ntt> Pattern forming method
US4506005A (en) 1983-05-10 1985-03-19 Gca Corporation Method of catalytic etching
EP0386518B1 (de) * 1989-02-23 1999-06-09 Seiko Epson Corporation Ätzverfahren für Verbindungshalbleiter
EP0714119B1 (de) * 1990-05-09 2002-12-04 Canon Kabushiki Kaisha Verfahren zur Erzeugung einer Struktur und Verfahren zum Vorbereiten einer halbleitenden Anordnung mit Hilfe dieses Verfahrens
JPH04199887A (ja) * 1990-11-29 1992-07-21 Matsushita Electric Ind Co Ltd ｐｎ接合素子及びその製造方法並びに青色発光ダイオード素子
KR100268926B1 (ko) * 1996-12-31 2000-10-16 김영환 반도체소자의 배선 형성방법
US6291356B1 (en) * 1997-12-08 2001-09-18 Applied Materials, Inc. Method for etching silicon oxynitride and dielectric antireflection coatings
US6177353B1 (en) * 1998-09-15 2001-01-23 Infineon Technologies North America Corp. Metallization etching techniques for reducing post-etch corrosion of metal lines
US6251568B1 (en) * 1999-02-09 2001-06-26 Conexant Systems Inc. Methods and apparatus for stripping photoresist and polymer layers from a semiconductor stack in a non-corrosive environment
JP2001110663A (ja) * 1999-10-08 2001-04-20 Hitachi Ltd 試料の処理方法および処理装置並びに磁気ヘッドの製作方法
JP4947849B2 (ja) * 2001-05-30 2012-06-06 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US6448576B1 (en) * 2001-08-30 2002-09-10 Bae Systems Information And Electronic Systems Integration, Inc. Programmable chalcogenide fuse within a semiconductor device
US6545287B2 (en) * 2001-09-07 2003-04-08 Intel Corporation Using selective deposition to form phase-change memory cells
US6831019B1 (en) * 2002-08-29 2004-12-14 Micron Technology, Inc. Plasma etching methods and methods of forming memory devices comprising a chalcogenide comprising layer received operably proximate conductive electrodes

Also Published As

Publication number Publication date
US20050032374A1 (en) 2005-02-10
US7256130B2 (en) 2007-08-14
DE60310528T2 (de) 2007-09-27
EP1475848B1 (de) 2006-12-20
EP1475848A1 (de) 2004-11-10

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