DE60318086D1 - System und methode zur reduzierung von leitungsverzögerung oder überlastung bei der synthese von hardware-solvern - Google Patents

System und methode zur reduzierung von leitungsverzögerung oder überlastung bei der synthese von hardware-solvern

Info

Publication number
DE60318086D1
DE60318086D1 DE60318086T DE60318086T DE60318086D1 DE 60318086 D1 DE60318086 D1 DE 60318086D1 DE 60318086 T DE60318086 T DE 60318086T DE 60318086 T DE60318086 T DE 60318086T DE 60318086 D1 DE60318086 D1 DE 60318086D1
Authority
DE
Germany
Prior art keywords
solvern
overload
synthesis
hardware
line delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60318086T
Other languages
English (en)
Other versions
DE60318086T2 (de
Inventor
Darren Cronquist
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Publication of DE60318086D1 publication Critical patent/DE60318086D1/de
Application granted granted Critical
Publication of DE60318086T2 publication Critical patent/DE60318086T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
DE60318086T 2002-10-07 2003-10-03 System und methode zur reduzierung von leitungsverzögerung oder überlastung bei der synthese von hardware-solvern Expired - Lifetime DE60318086T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US266719 1988-11-03
US10/266,719 US7107568B2 (en) 2002-10-07 2002-10-07 System and method for reducing wire delay or congestion during synthesis of hardware solvers
PCT/US2003/031619 WO2004034291A2 (en) 2002-10-07 2003-10-03 A system and method for reducing wire delay or congestion during synthesis of hardware solvers

Publications (2)

Publication Number Publication Date
DE60318086D1 true DE60318086D1 (de) 2008-01-24
DE60318086T2 DE60318086T2 (de) 2008-12-04

Family

ID=32042713

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60318086T Expired - Lifetime DE60318086T2 (de) 2002-10-07 2003-10-03 System und methode zur reduzierung von leitungsverzögerung oder überlastung bei der synthese von hardware-solvern

Country Status (6)

Country Link
US (1) US7107568B2 (de)
EP (1) EP1550059B1 (de)
JP (1) JP2006502502A (de)
AU (1) AU2003282708A1 (de)
DE (1) DE60318086T2 (de)
WO (1) WO2004034291A2 (de)

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Also Published As

Publication number Publication date
EP1550059A2 (de) 2005-07-06
WO2004034291A9 (en) 2006-05-26
AU2003282708A1 (en) 2004-05-04
WO2004034291A2 (en) 2004-04-22
DE60318086T2 (de) 2008-12-04
EP1550059B1 (de) 2007-12-12
US20040068331A1 (en) 2004-04-08
AU2003282708A8 (en) 2004-05-04
WO2004034291A3 (en) 2004-07-22
JP2006502502A (ja) 2006-01-19
US7107568B2 (en) 2006-09-12

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