DE60319125D1 - Integrierte schaltung mit mehreren betriebsarten - Google Patents

Integrierte schaltung mit mehreren betriebsarten

Info

Publication number
DE60319125D1
DE60319125D1 DE60319125T DE60319125T DE60319125D1 DE 60319125 D1 DE60319125 D1 DE 60319125D1 DE 60319125 T DE60319125 T DE 60319125T DE 60319125 T DE60319125 T DE 60319125T DE 60319125 D1 DE60319125 D1 DE 60319125D1
Authority
DE
Germany
Prior art keywords
integrated circuit
operating modes
several operating
circuitry
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60319125T
Other languages
English (en)
Other versions
DE60319125T2 (de
Inventor
Richard Beckett
Deif Atallah
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE60319125D1 publication Critical patent/DE60319125D1/de
Application granted granted Critical
Publication of DE60319125T2 publication Critical patent/DE60319125T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
DE60319125T 2002-11-20 2003-10-30 Integrierte schaltung mit mehreren betriebsarten Expired - Lifetime DE60319125T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/301,027 US7543085B2 (en) 2002-11-20 2002-11-20 Integrated circuit having multiple modes of operation
US301027 2002-11-20
PCT/US2003/034803 WO2004046941A1 (en) 2002-11-20 2003-10-30 Integrated circuit having multiple modes of operation

Publications (2)

Publication Number Publication Date
DE60319125D1 true DE60319125D1 (de) 2008-03-27
DE60319125T2 DE60319125T2 (de) 2009-02-05

Family

ID=32297966

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60319125T Expired - Lifetime DE60319125T2 (de) 2002-11-20 2003-10-30 Integrierte schaltung mit mehreren betriebsarten

Country Status (8)

Country Link
US (2) US7543085B2 (de)
EP (1) EP1563390B1 (de)
CN (1) CN100555259C (de)
AT (1) ATE386295T1 (de)
AU (1) AU2003287421A1 (de)
DE (1) DE60319125T2 (de)
TW (1) TWI283352B (de)
WO (1) WO2004046941A1 (de)

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JP5564197B2 (ja) * 2009-04-23 2014-07-30 株式会社メガチップス メモリ制御装置、半導体メモリ装置、メモリシステム及びメモリ制御方法
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Also Published As

Publication number Publication date
US7543085B2 (en) 2009-06-02
US20050149793A1 (en) 2005-07-07
TWI283352B (en) 2007-07-01
AU2003287421A1 (en) 2004-06-15
TW200413936A (en) 2004-08-01
EP1563390A1 (de) 2005-08-17
WO2004046941A1 (en) 2004-06-03
US20040098518A1 (en) 2004-05-20
CN1714348A (zh) 2005-12-28
CN100555259C (zh) 2009-10-28
DE60319125T2 (de) 2009-02-05
US7421517B2 (en) 2008-09-02
EP1563390B1 (de) 2008-02-13
ATE386295T1 (de) 2008-03-15

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Legal Events

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