DE60324725D1 - Verfahren und Speicherstrukturen mit Tunnelübergangsanordnung als Bedienungselement - Google Patents

Verfahren und Speicherstrukturen mit Tunnelübergangsanordnung als Bedienungselement

Info

Publication number
DE60324725D1
DE60324725D1 DE60324725T DE60324725T DE60324725D1 DE 60324725 D1 DE60324725 D1 DE 60324725D1 DE 60324725 T DE60324725 T DE 60324725T DE 60324725 T DE60324725 T DE 60324725T DE 60324725 D1 DE60324725 D1 DE 60324725D1
Authority
DE
Germany
Prior art keywords
control element
tunnel junction
memory structures
junction arrangement
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60324725T
Other languages
English (en)
Inventor
Peter Fricke
Brocklin Andrew L Van
James E Ellenson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE60324725D1 publication Critical patent/DE60324725D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/10—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having two electrodes, e.g. diodes or MIM elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/22—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the metal-insulator-metal type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
DE60324725T 2002-04-02 2003-03-31 Verfahren und Speicherstrukturen mit Tunnelübergangsanordnung als Bedienungselement Expired - Lifetime DE60324725D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/116,497 US6967350B2 (en) 2002-04-02 2002-04-02 Memory structures
US10/236,274 US6711045B2 (en) 2002-04-02 2002-09-06 Methods and memory structures using tunnel-junction device as control element

Publications (1)

Publication Number Publication Date
DE60324725D1 true DE60324725D1 (de) 2009-01-02

Family

ID=28041088

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60324725T Expired - Lifetime DE60324725D1 (de) 2002-04-02 2003-03-31 Verfahren und Speicherstrukturen mit Tunnelübergangsanordnung als Bedienungselement

Country Status (7)

Country Link
US (2) US6967350B2 (de)
EP (1) EP1351306A2 (de)
JP (1) JP2004006777A (de)
KR (1) KR20030079732A (de)
CN (1) CN1452248A (de)
DE (1) DE60324725D1 (de)
TW (1) TW200305273A (de)

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US6967350B2 (en) * 2002-04-02 2005-11-22 Hewlett-Packard Development Company, L.P. Memory structures
US6821848B2 (en) * 2002-04-02 2004-11-23 Hewlett-Packard Development Company, L.P. Tunnel-junction structures and methods
US6818549B2 (en) * 2003-03-05 2004-11-16 Hewlett-Packard Development Company, L.P. Buried magnetic tunnel-junction memory cell and methods
US6858883B2 (en) * 2003-06-03 2005-02-22 Hewlett-Packard Development Company, L.P. Partially processed tunnel junction control element
US7095644B2 (en) * 2003-12-22 2006-08-22 Unity Semiconductor Corporation Conductive memory array having page mode and burst mode read capability
US7099179B2 (en) * 2003-12-22 2006-08-29 Unity Semiconductor Corporation Conductive memory array having page mode and burst mode write capability
DE102004014435A1 (de) * 2004-03-24 2005-11-17 Siemens Ag Anordnung mit einem integrierten Schaltkreis
US7485540B2 (en) * 2005-08-18 2009-02-03 International Business Machines Corporation Integrated BEOL thin film resistor
KR100764056B1 (ko) * 2006-09-14 2007-10-08 삼성전자주식회사 상변화 기억 장치 및 그 제조 방법
KR101046852B1 (ko) 2006-10-16 2011-07-06 파나소닉 주식회사 비휘발성 기억소자 및 그 제조방법
WO2009063645A1 (ja) * 2007-11-15 2009-05-22 Panasonic Corporation 不揮発性記憶装置およびその製造方法
JP5159270B2 (ja) * 2007-11-22 2013-03-06 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
KR20110080153A (ko) * 2008-10-08 2011-07-12 더 리젠츠 오브 더 유니버시티 오브 미시건 저항을 조정할 수 있는 실리콘계 나노 스케일 저항 디바이스
KR20100041155A (ko) * 2008-10-13 2010-04-22 삼성전자주식회사 저항성 메모리 소자
US8586959B2 (en) * 2010-04-28 2013-11-19 Hewlett-Packard Development Company, L.P. Memristive switch device
CN103262240B (zh) * 2011-02-23 2016-08-03 松下知识产权经营株式会社 非易失性存储元件及其制造方法
US20130149815A1 (en) * 2011-09-16 2013-06-13 Hideaki Murase Nonvolatile memory element manufacturing method and nonvolatile memory element
CN108630810B (zh) * 2018-05-14 2022-07-19 中国科学院微电子研究所 1s1r存储器集成结构及其制备方法

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US6821848B2 (en) * 2002-04-02 2004-11-23 Hewlett-Packard Development Company, L.P. Tunnel-junction structures and methods
US6967350B2 (en) * 2002-04-02 2005-11-22 Hewlett-Packard Development Company, L.P. Memory structures
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Also Published As

Publication number Publication date
US6711045B2 (en) 2004-03-23
CN1452248A (zh) 2003-10-29
US20030185034A1 (en) 2003-10-02
KR20030079732A (ko) 2003-10-10
US20030183849A1 (en) 2003-10-02
US6967350B2 (en) 2005-11-22
EP1351306A2 (de) 2003-10-08
JP2004006777A (ja) 2004-01-08
TW200305273A (en) 2003-10-16

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, US

8328 Change in the person/name/address of the agent

Representative=s name: SCHOPPE, ZIMMERMANN, STOECKELER & ZINKLER, 82049 P

8364 No opposition during term of opposition