DE681324T1 - Verfahren zur Herstellung einer Feldoxyd-Zone mit unterliegender selbst-alignierten Feldimplantation unter Verwendung einer Niedrigtemperatur-Oxydschicht. - Google Patents

Verfahren zur Herstellung einer Feldoxyd-Zone mit unterliegender selbst-alignierten Feldimplantation unter Verwendung einer Niedrigtemperatur-Oxydschicht.

Info

Publication number
DE681324T1
DE681324T1 DE0681324T DE95302990T DE681324T1 DE 681324 T1 DE681324 T1 DE 681324T1 DE 0681324 T DE0681324 T DE 0681324T DE 95302990 T DE95302990 T DE 95302990T DE 681324 T1 DE681324 T1 DE 681324T1
Authority
DE
Germany
Prior art keywords
field
producing
low
oxide layer
implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE0681324T
Other languages
English (en)
Inventor
Mike F Chang
David G Grasso
Jun-Wei Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vishay Siliconix Inc
Original Assignee
Siliconix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconix Inc filed Critical Siliconix Inc
Publication of DE681324T1 publication Critical patent/DE681324T1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
DE0681324T 1994-05-02 1995-05-02 Verfahren zur Herstellung einer Feldoxyd-Zone mit unterliegender selbst-alignierten Feldimplantation unter Verwendung einer Niedrigtemperatur-Oxydschicht. Pending DE681324T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/236,299 US5439842A (en) 1992-09-21 1994-05-02 Low temperature oxide layer over field implant mask

Publications (1)

Publication Number Publication Date
DE681324T1 true DE681324T1 (de) 1996-08-29

Family

ID=22888949

Family Applications (1)

Application Number Title Priority Date Filing Date
DE0681324T Pending DE681324T1 (de) 1994-05-02 1995-05-02 Verfahren zur Herstellung einer Feldoxyd-Zone mit unterliegender selbst-alignierten Feldimplantation unter Verwendung einer Niedrigtemperatur-Oxydschicht.

Country Status (4)

Country Link
US (1) US5439842A (de)
EP (1) EP0681324A3 (de)
JP (1) JPH07307305A (de)
DE (1) DE681324T1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6268242B1 (en) * 1997-12-31 2001-07-31 Richard K. Williams Method of forming vertical mosfet device having voltage clamped gate and self-aligned contact
US6172383B1 (en) 1997-12-31 2001-01-09 Siliconix Incorporated Power MOSFET having voltage-clamped gate
DE10027397A1 (de) * 2000-06-02 2001-12-13 Graffinity Pharm Design Gmbh Oberfläche zur Immobilisierung von Liganden
US7825488B2 (en) 2006-05-31 2010-11-02 Advanced Analogic Technologies, Inc. Isolation structures for integrated circuits and modular methods of forming the same
US6855985B2 (en) * 2002-09-29 2005-02-15 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
JP4804734B2 (ja) * 2004-09-29 2011-11-02 オンセミコンダクター・トレーディング・リミテッド 半導体装置の製造方法
CN104238262A (zh) * 2013-06-14 2014-12-24 深圳市力振半导体有限公司 一种用半导体晶圆片来制备的掩模版

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3853633A (en) * 1972-12-04 1974-12-10 Motorola Inc Method of making a semi planar insulated gate field-effect transistor device with implanted field
CA1001771A (en) * 1973-01-15 1976-12-14 Fairchild Camera And Instrument Corporation Method of mos transistor manufacture and resulting structure
JPS5286083A (en) * 1976-01-12 1977-07-16 Hitachi Ltd Production of complimentary isolation gate field effect transistor
IT1166587B (it) * 1979-01-22 1987-05-05 Ates Componenti Elettron Processo per la fabbricazione di transistori mos complementari ad alta integrazione per tensioni elevate
US4373965A (en) * 1980-12-22 1983-02-15 Ncr Corporation Suppression of parasitic sidewall transistors in locos structures
US4391650A (en) * 1980-12-22 1983-07-05 Ncr Corporation Method for fabricating improved complementary metal oxide semiconductor devices
FR2579828A1 (fr) * 1985-03-29 1986-10-03 Thomson Csf Procede d'oxydation localisee pour l'obtention d'oxyde epais
IT1200725B (it) * 1985-08-28 1989-01-27 Sgs Microelettronica Spa Struttura di isolamento in dispositivi mos e procedimento di preparazione della stessa
GB2186117B (en) * 1986-01-30 1989-11-01 Sgs Microelettronica Spa Monolithically integrated semiconductor device containing bipolar junction,cmosand dmos transistors and low leakage diodes and a method for its fabrication
US4879583A (en) * 1986-03-03 1989-11-07 Rockwell International Corporation Diffused field CMOS-bulk process and CMOS transistors
US4829019A (en) * 1987-05-12 1989-05-09 Texas Instruments Incorporated Method for increasing source/drain to channel stop breakdown and decrease P+/N+ encroachment
US4812418A (en) * 1987-11-27 1989-03-14 Motorola, Inc. Micron and submicron patterning without using a lithographic mask having submicron dimensions
US4912062A (en) * 1988-05-20 1990-03-27 Motorola, Inc. Method of eliminating bird's beaks when forming field oxide without nitride mask
US5156989A (en) * 1988-11-08 1992-10-20 Siliconix, Incorporated Complementary, isolated DMOS IC technology
EP0434182B1 (de) * 1989-12-22 2002-04-03 Samsung Semiconductor, Inc. Verfahren zur Herstellung vergrabener Zonen für integrierte Schaltungen
JPH04348053A (ja) * 1991-05-24 1992-12-03 Nippon Steel Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0681324A3 (de) 1996-12-27
EP0681324A2 (de) 1995-11-08
JPH07307305A (ja) 1995-11-21
US5439842A (en) 1995-08-08

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