DE68909111T2 - Elektronisches Modul, das Substratelemente enthält. - Google Patents

Elektronisches Modul, das Substratelemente enthält.

Info

Publication number
DE68909111T2
DE68909111T2 DE89201273T DE68909111T DE68909111T2 DE 68909111 T2 DE68909111 T2 DE 68909111T2 DE 89201273 T DE89201273 T DE 89201273T DE 68909111 T DE68909111 T DE 68909111T DE 68909111 T2 DE68909111 T2 DE 68909111T2
Authority
DE
Germany
Prior art keywords
electronic module
substrate elements
contains substrate
elements
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE89201273T
Other languages
English (en)
Other versions
DE68909111D1 (de
Inventor
Wilhelm Albert Sauerwald
Anwar Osseyran
Lars Arjen Raoul Eerenstein
Jong Franciscus Gerardus Ma De
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of DE68909111D1 publication Critical patent/DE68909111D1/de
Publication of DE68909111T2 publication Critical patent/DE68909111T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536Scan chain arrangements, e.g. connections, test bus, analog signals
    • G01R31/318538Topological or mechanical aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
DE89201273T 1988-05-27 1989-05-22 Elektronisches Modul, das Substratelemente enthält. Expired - Fee Related DE68909111T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8801362A NL8801362A (nl) 1988-05-27 1988-05-27 Elektronische module bevattende een eerste substraatelement met een funktioneel deel, alsmede een tweede substraatelement voor het testen van een interkonnektiefunktie, voet bevattende zo een tweede substraatelement, substraatelement te gebruiken als zo een tweede substraatelement en elektronisch apparaat bevattende een plaat met gedrukte bedrading en ten minste twee zulke elektronische modules.

Publications (2)

Publication Number Publication Date
DE68909111D1 DE68909111D1 (de) 1993-10-21
DE68909111T2 true DE68909111T2 (de) 1994-03-31

Family

ID=19852363

Family Applications (1)

Application Number Title Priority Date Filing Date
DE89201273T Expired - Fee Related DE68909111T2 (de) 1988-05-27 1989-05-22 Elektronisches Modul, das Substratelemente enthält.

Country Status (6)

Country Link
US (1) US4967142A (de)
EP (1) EP0344834B1 (de)
JP (1) JP2857764B2 (de)
KR (1) KR0163756B1 (de)
DE (1) DE68909111T2 (de)
NL (1) NL8801362A (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2561164B2 (ja) * 1990-02-26 1996-12-04 三菱電機株式会社 半導体集積回路
US5159598A (en) * 1990-05-03 1992-10-27 General Electric Company Buffer integrated circuit providing testing interface
JPH04212524A (ja) * 1990-12-06 1992-08-04 Matsushita Electric Ind Co Ltd 半導体集積回路
TW216472B (de) * 1991-12-18 1993-11-21 Philips Nv
US5410551A (en) * 1992-01-02 1995-04-25 Andahl Corporation Net verification method and apparatus
US5448166A (en) * 1992-01-03 1995-09-05 Hewlett-Packard Company Powered testing of mixed conventional/boundary-scan logic
US5260649A (en) * 1992-01-03 1993-11-09 Hewlett-Packard Company Powered testing of mixed conventional/boundary-scan logic
TW253097B (de) * 1992-03-02 1995-08-01 At & T Corp
US5285152A (en) * 1992-03-23 1994-02-08 Ministar Peripherals International Limited Apparatus and methods for testing circuit board interconnect integrity
US5534774A (en) * 1992-04-23 1996-07-09 Intel Corporation Apparatus for a test access architecture for testing of modules within integrated circuits
US5471481A (en) * 1992-05-18 1995-11-28 Sony Corporation Testing method for electronic apparatus
US5809036A (en) * 1993-11-29 1998-09-15 Motorola, Inc. Boundary-scan testable system and method
DE69433618T2 (de) * 1993-12-16 2005-02-03 Koninklijke Philips Electronics N.V. Gerät zur prüfung der verbindung zwischen dem ausgang einer schaltung mit fester logischer ausgabe und dem eingang eines weiteren schaltkreises
US5787098A (en) * 1996-07-29 1998-07-28 International Business Machines Corporation Complete chip I/O test through low contact testing using enhanced boundary scan
US5974578A (en) * 1996-08-06 1999-10-26 Matsushita Electronics Corporation Integrated circuit and test method therefor
US6114870A (en) * 1996-10-04 2000-09-05 Texas Instruments Incorporated Test system and process with a microcomputer at each test location
US6617872B2 (en) * 1996-10-04 2003-09-09 Texas Instruments Incorporated Reduced cost, high speed integrated circuit test arrangement
US6199182B1 (en) * 1997-03-27 2001-03-06 Texas Instruments Incorporated Probeless testing of pad buffers on wafer
US5963464A (en) * 1998-02-26 1999-10-05 International Business Machines Corporation Stackable memory card
GB2344184A (en) 1998-11-26 2000-05-31 Ericsson Telefon Ab L M Testing integrated circuits
JP4887552B2 (ja) * 2000-07-04 2012-02-29 富士通セミコンダクター株式会社 Lsiチップのレイアウト設計方法
US6731128B2 (en) * 2000-07-13 2004-05-04 International Business Machines Corporation TFI probe I/O wrap test method
WO2002080268A1 (en) * 2001-03-30 2002-10-10 Infineon Technologies Ag A substrate for mounting a semiconductor chip
JP2004519684A (ja) * 2001-04-09 2004-07-02 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 電源試験インタフェースを備えた集積回路
DE102004014242B4 (de) * 2004-03-24 2014-05-28 Qimonda Ag Integrierter Baustein mit mehreren voneinander getrennten Substraten
JP2006200983A (ja) * 2005-01-19 2006-08-03 Denso Corp 半導体集積回路装置およびその試験方法
US8991829B2 (en) 2007-11-20 2015-03-31 The Timken Company Non-contact labyrinth seal assembly and method of construction thereof
KR101014965B1 (ko) 2008-11-03 2011-02-16 유수엽 임베디드 보드 개발 및 교육용 보드유닛
JP2013142434A (ja) 2012-01-10 2013-07-22 Showa Corp 軸受構造体

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1003048B (it) * 1972-03-17 1976-06-10 Honeywell Inf Systems Dispositivo per verificare il cor retto comportamento di unita circui tali integrate sequenziali
US4145620A (en) * 1977-10-05 1979-03-20 Serel Corporation Modular dynamic burn-in apparatus
US4567432A (en) * 1983-06-09 1986-01-28 Texas Instruments Incorporated Apparatus for testing integrated circuits
DE3578224D1 (de) * 1984-07-27 1990-07-19 Fujitsu Ltd Integrierte schaltung vom chip-auf-chip-typ.
FR2569411B1 (fr) * 1984-08-23 1986-11-21 Charbonnages Ste Chimique Nouveau procede de fabrication de terpolymeres radicalaires de l'ethylene et de copolymeres radicalaires de l'ethylene
NL8502476A (nl) * 1985-09-11 1987-04-01 Philips Nv Werkwijze voor het testen van dragers met meerdere digitaal-werkende geintegreerde schakelingen, drager voorzien van zulke schakelingen, geintegreerde schakeling geschikt voor het aanbrengen op zo'n drager, en testinrichting voor het testen van zulke dragers.
JPS63182585A (ja) * 1987-01-26 1988-07-27 Toshiba Corp テスト容易化機能を備えた論理回路
JPS63286781A (ja) * 1987-05-19 1988-11-24 Mitsubishi Electric Corp 回路の試験方法

Also Published As

Publication number Publication date
NL8801362A (nl) 1989-12-18
KR0163756B1 (ko) 1999-03-20
EP0344834B1 (de) 1993-09-15
KR890017546A (ko) 1989-12-16
EP0344834A1 (de) 1989-12-06
JP2857764B2 (ja) 1999-02-17
JPH0225774A (ja) 1990-01-29
US4967142A (en) 1990-10-30
DE68909111D1 (de) 1993-10-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8339 Ceased/non-payment of the annual fee