DE68916120T2 - Verfahren zur Herstellung einer integrierten Speicher-Zelle. - Google Patents

Verfahren zur Herstellung einer integrierten Speicher-Zelle.

Info

Publication number
DE68916120T2
DE68916120T2 DE68916120T DE68916120T DE68916120T2 DE 68916120 T2 DE68916120 T2 DE 68916120T2 DE 68916120 T DE68916120 T DE 68916120T DE 68916120 T DE68916120 T DE 68916120T DE 68916120 T2 DE68916120 T2 DE 68916120T2
Authority
DE
Germany
Prior art keywords
manufacturing
memory cell
integrated memory
integrated
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68916120T
Other languages
English (en)
Other versions
DE68916120D1 (de
Inventor
Pierre Jeuch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Application granted granted Critical
Publication of DE68916120D1 publication Critical patent/DE68916120D1/de
Publication of DE68916120T2 publication Critical patent/DE68916120T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
DE68916120T 1988-07-13 1989-07-12 Verfahren zur Herstellung einer integrierten Speicher-Zelle. Expired - Lifetime DE68916120T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8809559A FR2634318B1 (fr) 1988-07-13 1988-07-13 Procede de fabrication d'une cellule de memoire integree

Publications (2)

Publication Number Publication Date
DE68916120D1 DE68916120D1 (de) 1994-07-21
DE68916120T2 true DE68916120T2 (de) 1995-02-02

Family

ID=9368432

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68916120T Expired - Lifetime DE68916120T2 (de) 1988-07-13 1989-07-12 Verfahren zur Herstellung einer integrierten Speicher-Zelle.

Country Status (5)

Country Link
US (1) US5011787A (de)
EP (1) EP0351316B1 (de)
JP (1) JP3021472B2 (de)
DE (1) DE68916120T2 (de)
FR (1) FR2634318B1 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1229131B (it) * 1989-03-09 1991-07-22 Sgs Thomson Microelectronics Matrice di memoria eprom con struttura a tovaglia e procedimento per la sua fabbricazione.
US5196914A (en) * 1989-03-15 1993-03-23 Sgs-Thomson Microelectronics S.R.L. Table cloth matrix of EPROM memory cells with an asymmetrical fin
JP2565213B2 (ja) * 1989-10-27 1996-12-18 ソニー株式会社 読み出し専用メモリ装置
US5223458A (en) * 1990-12-18 1993-06-29 Raytheon Company Method of manufacturing a III-V semiconductor device using a self-biased substrate and a plasma containing an electronegative species
US5880483A (en) * 1990-12-18 1999-03-09 Shanfield; Stanley R. Semiconductor devices
US5712180A (en) * 1992-01-14 1998-01-27 Sundisk Corporation EEPROM with split gate source side injection
US6222762B1 (en) * 1992-01-14 2001-04-24 Sandisk Corporation Multi-state memory
US7071060B1 (en) * 1996-02-28 2006-07-04 Sandisk Corporation EEPROM with split gate source side infection with sidewall spacers
WO1995022837A1 (en) * 1994-02-17 1995-08-24 National Semiconductor Corporation A method for reducing the spacing between the horizontally-adjacent floating gates of a flash eprom array
US5808874A (en) * 1996-05-02 1998-09-15 Tessera, Inc. Microelectronic connections with liquid conductive elements
US6127698A (en) * 1998-03-23 2000-10-03 Texas Instruments - Acer Incorporated High density/speed nonvolatile memories with a textured tunnel oxide and a high capacitive-coupling ratio
KR100314127B1 (ko) * 1999-04-22 2001-11-17 윤종용 반도체소자의 부유게이트 형성방법
US6576949B1 (en) 1999-08-30 2003-06-10 Advanced Micro Devices, Inc. Integrated circuit having optimized gate coupling capacitance
US6682978B1 (en) 1999-08-30 2004-01-27 Advanced Micro Devices, Inc. Integrated circuit having increased gate coupling capacitance
US6232635B1 (en) 2000-04-06 2001-05-15 Advanced Micro Devices, Inc. Method to fabricate a high coupling flash cell with less silicide seam problem
US6242306B1 (en) 2000-07-28 2001-06-05 Advanced Micro Devices Dual bit isolation scheme for flash memory devices having polysilicon floating gates
US7749818B2 (en) * 2002-01-28 2010-07-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
TWI261358B (en) * 2002-01-28 2006-09-01 Semiconductor Energy Lab Semiconductor device and method of manufacturing the same
TWI272666B (en) * 2002-01-28 2007-02-01 Semiconductor Energy Lab Semiconductor device and method of manufacturing the same
EP1435657A1 (de) * 2002-12-30 2004-07-07 STMicroelectronics S.r.l. Festwertspeicherzelle und Herstellungsverfahren

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS583380B2 (ja) * 1977-03-04 1983-01-21 株式会社日立製作所 半導体装置とその製造方法
NL7702814A (nl) * 1977-03-16 1978-09-19 Philips Nv Halfgeleiderinrichting en werkwijze ter ver- vaardiging daarvan.
US4409723A (en) * 1980-04-07 1983-10-18 Eliyahou Harari Method of forming non-volatile EPROM and EEPROM with increased efficiency
US4359816A (en) * 1980-07-08 1982-11-23 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits
US4373250A (en) * 1980-11-17 1983-02-15 Signetics Corporation Process for fabricating a high capacity memory cell
US4402128A (en) * 1981-07-20 1983-09-06 Rca Corporation Method of forming closely spaced lines or contacts in semiconductor devices
JPS58158972A (ja) * 1982-03-16 1983-09-21 Toshiba Corp 半導体装置の製造方法
JPS58168258A (ja) * 1982-03-30 1983-10-04 Nippon Telegr & Teleph Corp <Ntt> 半導体集積回路装置およびその製造方法
JPS5957450A (ja) * 1982-09-27 1984-04-03 Nec Corp 半導体装置の素子分離方法
JPS5974677A (ja) * 1982-10-22 1984-04-27 Ricoh Co Ltd 半導体装置及びその製造方法
JPS59201461A (ja) * 1983-04-28 1984-11-15 Toshiba Corp 読み出し専用半導体記憶装置およびその製造方法
JPS60149145A (ja) * 1983-12-14 1985-08-06 Nec Corp 半導体装置の製造方法
DE3575813D1 (de) * 1984-05-07 1990-03-08 Toshiba Kawasaki Kk Verfahren zum herstellen einer halbleiteranordnung mit einer gateelektrodenstapel-struktur.
JPH0810726B2 (ja) * 1984-07-06 1996-01-31 株式会社東芝 半導体装置の製造方法
JPS6150370A (ja) * 1984-08-20 1986-03-12 Toshiba Corp 半導体装置の製造方法
JPS61139986A (ja) * 1984-12-11 1986-06-27 Hitachi Maxell Ltd デイスクカ−トリツジの製造方法、およびデイスクカ−トリツジの自動組立装置
US4597060A (en) * 1985-05-01 1986-06-24 Texas Instruments Incorporated EPROM array and method for fabricating
JPH0736437B2 (ja) * 1985-11-29 1995-04-19 株式会社日立製作所 半導体メモリの製造方法
US4698900A (en) * 1986-03-27 1987-10-13 Texas Instruments Incorporated Method of making a non-volatile memory having dielectric filled trenches
FR2603128B1 (fr) * 1986-08-21 1988-11-10 Commissariat Energie Atomique Cellule de memoire eprom et son procede de fabrication
US4749443A (en) * 1986-12-04 1988-06-07 Texas Instruments Incorporated Sidewall oxide to reduce filaments
FR2618011B1 (fr) * 1987-07-10 1992-09-18 Commissariat Energie Atomique Procede de fabrication d'une cellule de memoire
JPS6450439A (en) * 1987-08-21 1989-02-27 Oki Electric Ind Co Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
FR2634318B1 (fr) 1992-02-21
EP0351316A1 (de) 1990-01-17
JP3021472B2 (ja) 2000-03-15
US5011787A (en) 1991-04-30
JPH02125668A (ja) 1990-05-14
DE68916120D1 (de) 1994-07-21
EP0351316B1 (de) 1994-06-15
FR2634318A1 (fr) 1990-01-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition