DE68916818D1 - Zur internen Erzeugung eines Schreibsignals fähige Halbleiterspeicheranordnung. - Google Patents

Zur internen Erzeugung eines Schreibsignals fähige Halbleiterspeicheranordnung.

Info

Publication number
DE68916818D1
DE68916818D1 DE68916818T DE68916818T DE68916818D1 DE 68916818 D1 DE68916818 D1 DE 68916818D1 DE 68916818 T DE68916818 T DE 68916818T DE 68916818 T DE68916818 T DE 68916818T DE 68916818 D1 DE68916818 D1 DE 68916818D1
Authority
DE
Germany
Prior art keywords
generating
semiconductor memory
write signal
memory arrangement
arrangement capable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68916818T
Other languages
English (en)
Inventor
Atsushi Suzuki
Kazuya Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63021161A external-priority patent/JP2509275B2/ja
Priority claimed from JP63056311A external-priority patent/JP2528930B2/ja
Priority claimed from JP63056314A external-priority patent/JPH01232597A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE68916818D1 publication Critical patent/DE68916818D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109Control signal input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087Data input latches
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093Input synchronization
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
DE68916818T 1988-02-02 1989-02-02 Zur internen Erzeugung eines Schreibsignals fähige Halbleiterspeicheranordnung. Expired - Lifetime DE68916818D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP63021161A JP2509275B2 (ja) 1988-02-02 1988-02-02 半導体メモリ装置
JP63056311A JP2528930B2 (ja) 1988-03-11 1988-03-11 半導体メモリ装置
JP63056314A JPH01232597A (ja) 1988-03-11 1988-03-11 半導体メモリ装置

Publications (1)

Publication Number Publication Date
DE68916818D1 true DE68916818D1 (de) 1994-08-25

Family

ID=27283313

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68916818T Expired - Lifetime DE68916818D1 (de) 1988-02-02 1989-02-02 Zur internen Erzeugung eines Schreibsignals fähige Halbleiterspeicheranordnung.

Country Status (4)

Country Link
US (1) US4916670A (de)
EP (1) EP0327463B1 (de)
KR (1) KR920008029B1 (de)
DE (1) DE68916818D1 (de)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6112287A (en) * 1993-03-01 2000-08-29 Busless Computers Sarl Shared memory multiprocessor system using a set of serial links as processors-memory switch
KR940008295B1 (ko) * 1989-08-28 1994-09-10 가부시기가이샤 히다찌세이사꾸쇼 반도체메모리
USRE38379E1 (en) * 1989-08-28 2004-01-06 Hitachi, Ltd. Semiconductor memory with alternately multiplexed row and column addressing
US5022011A (en) * 1989-12-28 1991-06-04 Inova Microelectronics Corporation Apparatus and method for reducing the access time after a write operation in a static memory device
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
US5995443A (en) * 1990-04-18 1999-11-30 Rambus Inc. Synchronous memory device
JP3992757B2 (ja) * 1991-04-23 2007-10-17 テキサス インスツルメンツ インコーポレイテツド マイクロプロセッサと同期するメモリ、及びデータプロセッサ、同期メモリ、周辺装置とシステムクロックを含むシステム
US5268863A (en) * 1992-07-06 1993-12-07 Motorola, Inc. Memory having a write enable controlled word line
US5655113A (en) * 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
US5548797A (en) * 1994-10-03 1996-08-20 International Business Machines Corporation Digital clock pulse positioning circuit for delaying a signal input by a fist time duration and a second time duration to provide a positioned clock signal
US6810449B1 (en) 1995-10-19 2004-10-26 Rambus, Inc. Protocol for communication with dynamic memory
US6470405B2 (en) 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US6115321A (en) * 1997-06-17 2000-09-05 Texas Instruments Incorporated Synchronous dynamic random access memory with four-bit data prefetch
US6266379B1 (en) 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
KR100253592B1 (ko) * 1997-06-30 2000-04-15 김영환 클럭동기 래치회로
US6401167B1 (en) * 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
WO1999019805A1 (en) * 1997-10-10 1999-04-22 Rambus Incorporated Method and apparatus for two step memory write operations
US6240047B1 (en) 1998-07-06 2001-05-29 Texas Instruments Incorporated Synchronous dynamic random access memory with four-bit data prefetch
US6651199B1 (en) * 2000-06-22 2003-11-18 Xilinx, Inc. In-system programmable flash memory device with trigger circuit for generating limited duration program instruction
US6392957B1 (en) * 2000-11-28 2002-05-21 Virage Logic Corporation Fast read/write cycle memory device having a self-timed read/write control circuit
US6445640B1 (en) * 2001-03-23 2002-09-03 Sun Microsystems, Inc. Method and apparatus for invalidating memory array write operations
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US8391039B2 (en) * 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US7333357B2 (en) * 2003-12-11 2008-02-19 Texas Instruments Incorproated Static random access memory device having reduced leakage current during active mode and a method of operating thereof
US7301831B2 (en) 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
JP4957719B2 (ja) * 2006-02-28 2012-06-20 富士通株式会社 Ramマクロ、そのタイミング生成回路
DE102008048066B4 (de) 2008-09-19 2018-02-01 Texas Instruments Deutschland Gmbh Zugriffssteuerschaltung zur Verwendung mit einer Überwachungs-Logikschaltungsanordnung in einem Verfahren zum Schutz von Software für eingebettete Anwendungen vor unerlaubtem Zugriff
WO2014013298A1 (en) * 2012-07-20 2014-01-23 Freescale Semiconductor, Inc. Register file module and method therefor
KR102094393B1 (ko) 2013-11-18 2020-03-27 삼성전자주식회사 불휘발성 메모리 시스템 및 그것의 동작 방법
US10235481B2 (en) 2014-02-05 2019-03-19 Yokogawa Corporation Of America System and method for online measurement of vapor pressure in hydrocarbon process streams

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6167154A (ja) * 1984-09-11 1986-04-07 Fujitsu Ltd 半導体記憶装置
JPS6488662A (en) * 1987-09-29 1989-04-03 Fujitsu Ltd Semiconductor memory

Also Published As

Publication number Publication date
KR890013648A (ko) 1989-09-25
EP0327463A2 (de) 1989-08-09
EP0327463B1 (de) 1994-07-20
EP0327463A3 (de) 1991-04-03
KR920008029B1 (en) 1992-09-21
US4916670A (en) 1990-04-10

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Legal Events

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