DE68923573D1 - Eingangsschaltungen. - Google Patents

Eingangsschaltungen.

Info

Publication number
DE68923573D1
DE68923573D1 DE68923573T DE68923573T DE68923573D1 DE 68923573 D1 DE68923573 D1 DE 68923573D1 DE 68923573 T DE68923573 T DE 68923573T DE 68923573 T DE68923573 T DE 68923573T DE 68923573 D1 DE68923573 D1 DE 68923573D1
Authority
DE
Germany
Prior art keywords
input circuits
circuits
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68923573T
Other languages
English (en)
Other versions
DE68923573T2 (de
Inventor
Yoichi C O Patents Div Nishino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63079558A external-priority patent/JP2797312B2/ja
Priority claimed from JP18599588A external-priority patent/JPH0234969A/ja
Application filed by Sony Corp filed Critical Sony Corp
Application granted granted Critical
Publication of DE68923573D1 publication Critical patent/DE68923573D1/de
Publication of DE68923573T2 publication Critical patent/DE68923573T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
DE68923573T 1988-03-31 1989-03-30 Eingangsschaltungen. Expired - Lifetime DE68923573T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63079558A JP2797312B2 (ja) 1988-03-31 1988-03-31 入出力回路
JP18599588A JPH0234969A (ja) 1988-07-25 1988-07-25 入力保護回路

Publications (2)

Publication Number Publication Date
DE68923573D1 true DE68923573D1 (de) 1995-08-31
DE68923573T2 DE68923573T2 (de) 1996-01-18

Family

ID=26420579

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68923573T Expired - Lifetime DE68923573T2 (de) 1988-03-31 1989-03-30 Eingangsschaltungen.

Country Status (3)

Country Link
US (1) US5025419A (de)
EP (1) EP0335715B1 (de)
DE (1) DE68923573T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2078173B1 (es) * 1993-12-30 1998-01-16 Alcatel Standard Electrica Arquitectura de circuitos integrados digitales.
JP2783214B2 (ja) * 1995-09-18 1998-08-06 日本電気株式会社 半導体メモリ装置
JPH10188556A (ja) * 1996-12-20 1998-07-21 Fujitsu Ltd 半導体記憶装置
US6256224B1 (en) * 2000-05-03 2001-07-03 Hewlett-Packard Co Write circuit for large MRAM arrays
FR2765719B1 (fr) * 1997-07-04 1999-10-01 Sgs Thomson Microelectronics Perfectionnement aux memoires a acces sequentiels
KR100287190B1 (ko) 1999-04-07 2001-04-16 윤종용 선택되는 메모리 모듈만을 데이터 라인에 연결하는 메모리 모듈 시스템 및 이를 이용한 데이터 입출력 방법
US6236611B1 (en) * 1999-12-20 2001-05-22 Motorola, Inc. Peak program current reduction apparatus and method
JP2001185721A (ja) 1999-12-22 2001-07-06 Nec Corp 半導体装置
DE10002082A1 (de) * 2000-01-19 2001-08-02 Infineon Technologies Ag Schaltungsanordnung mit variabler Anzahl von Datenausgängen und Vorrichtung zum Auslesen von Daten aus einer Schaltungsanordnung mit variabler Anzahl von Datenausgängen
NO20004236L (no) * 2000-08-24 2002-02-25 Thin Film Electronics Asa Ikke-flyktig passiv matriseinnretning og fremgangsmåte for utlesing av samme
US6845461B1 (en) * 2001-11-20 2005-01-18 Silicon Image, Inc. High-speed bus with embedded clock signals
US6903584B2 (en) * 2002-03-08 2005-06-07 Stmicroelectronics, Inc. Circuit and method for detecting the state of a switch

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3819952A (en) * 1973-01-29 1974-06-25 Mitsubishi Electric Corp Semiconductor device
US4527213A (en) * 1981-11-27 1985-07-02 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor integrated circuit device with circuits for protecting an input section against an external surge
US4775990A (en) * 1984-01-18 1988-10-04 Sharp Kabushiki Kaisha Serial-to-parallel converter
US4800530A (en) * 1986-08-19 1989-01-24 Kabushiki Kasiha Toshiba Semiconductor memory system with dynamic random access memory cells

Also Published As

Publication number Publication date
DE68923573T2 (de) 1996-01-18
EP0335715B1 (de) 1995-07-26
EP0335715A2 (de) 1989-10-04
EP0335715A3 (de) 1992-03-25
US5025419A (en) 1991-06-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition