DE68926936T2 - Vorrichtung und Technik für Burstprogrammierung - Google Patents

Vorrichtung und Technik für Burstprogrammierung

Info

Publication number
DE68926936T2
DE68926936T2 DE68926936T DE68926936T DE68926936T2 DE 68926936 T2 DE68926936 T2 DE 68926936T2 DE 68926936 T DE68926936 T DE 68926936T DE 68926936 T DE68926936 T DE 68926936T DE 68926936 T2 DE68926936 T2 DE 68926936T2
Authority
DE
Germany
Prior art keywords
burst
column latch
counter
memory
memory controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68926936T
Other languages
English (en)
Other versions
DE68926936D1 (de
Inventor
Percy P Aria
David W Stoenner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE68926936D1 publication Critical patent/DE68926936D1/de
Application granted granted Critical
Publication of DE68926936T2 publication Critical patent/DE68926936T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode
DE68926936T 1988-06-24 1989-06-16 Vorrichtung und Technik für Burstprogrammierung Expired - Lifetime DE68926936T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/211,357 US5134699A (en) 1988-06-24 1988-06-24 Programmable burst data transfer apparatus and technique

Publications (2)

Publication Number Publication Date
DE68926936D1 DE68926936D1 (de) 1996-09-19
DE68926936T2 true DE68926936T2 (de) 1997-02-27

Family

ID=22786599

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68926936T Expired - Lifetime DE68926936T2 (de) 1988-06-24 1989-06-16 Vorrichtung und Technik für Burstprogrammierung

Country Status (7)

Country Link
US (1) US5134699A (de)
EP (1) EP0348113B1 (de)
JP (1) JP2992552B2 (de)
AT (1) ATE141424T1 (de)
DE (1) DE68926936T2 (de)
ES (1) ES2090037T3 (de)
GR (1) GR3020706T3 (de)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03254497A (ja) * 1990-03-05 1991-11-13 Mitsubishi Electric Corp マイクロコンピュータ
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US6324120B2 (en) 1990-04-18 2001-11-27 Rambus Inc. Memory device having a variable data output length
EP0994420B1 (de) † 1990-04-18 2006-01-04 Rambus Inc. DRAM Halbleiter Vorrichtung
GB9018993D0 (en) * 1990-08-31 1990-10-17 Ncr Co Work station interfacing means having burst mode capability
IT1241318B (it) * 1990-11-19 1994-01-10 Olivetti & Co Spa Dispositivo di indirizzamento di memoria
US5274786A (en) * 1990-11-28 1993-12-28 Hewlett-Packard Company Microprocessor memory bus interface for inhibiting relatching of row address portions upon subsequent accesses including a same row address portion
US5535354A (en) * 1991-03-11 1996-07-09 Digital Equipment Corporation Method for addressing a block addressable memory using a gray code
JP3105283B2 (ja) * 1991-03-20 2000-10-30 キヤノン株式会社 メモリ・アクセス制御装置
US5440751A (en) * 1991-06-21 1995-08-08 Compaq Computer Corp. Burst data transfer to single cycle data transfer conversion and strobe signal conversion
DE4292241C2 (de) * 1991-07-02 1998-04-16 Intel Corp Einrichtung und Verfahren zum sequentiellen Durchführen mehrerer Bustransaktionen zwischen einem Prozessor und vorinstallierten Speichermodulen in einem Computersystem
US5386579A (en) * 1991-09-16 1995-01-31 Integrated Device Technology, Inc. Minimum pin-count multiplexed address/data bus with byte enable and burst address counter support microprocessor transmitting byte enable signals on multiplexed address/data bus having burst address counter for supporting signal datum and burst transfer
US5291580A (en) * 1991-10-04 1994-03-01 Bull Hn Information Systems Inc. High performance burst read data transfer operation
US5345573A (en) * 1991-10-04 1994-09-06 Bull Hn Information Systems Inc. High speed burst read address generation with high speed transfer
US5572692A (en) * 1991-12-24 1996-11-05 Intel Corporation Memory configuration decoding system having automatic row base address generation mechanism for variable memory devices with row access interleaving
US5485589A (en) * 1991-12-31 1996-01-16 Dell Usa, L.P. Predictive addressing architecture
AU5987294A (en) * 1993-02-17 1994-09-14 3Com Corporation System for reading dynamically changing data
JP2875448B2 (ja) * 1993-03-17 1999-03-31 松下電器産業株式会社 データ転送装置及びマルチプロセッサシステム
CA2118662C (en) * 1993-03-22 1999-07-13 Paul A. Santeler Memory controller having all dram address and control signals provided synchronously from a single device
US5604884A (en) * 1993-03-22 1997-02-18 Compaq Computer Corporation Burst SRAMS for use with a high speed clock
US5861894A (en) * 1993-06-24 1999-01-19 Discovision Associates Buffer manager
GB2281137B (en) * 1993-08-20 1997-10-08 Advanced Risc Mach Ltd Data bus
US5590286A (en) * 1993-10-07 1996-12-31 Sun Microsystems, Inc. Method and apparatus for the pipelining of data during direct memory accesses
JP3579461B2 (ja) * 1993-10-15 2004-10-20 株式会社ルネサステクノロジ データ処理システム及びデータ処理装置
CA2145363C (en) * 1994-03-24 1999-07-13 Anthony Mark Jones Ram interface
JP3155144B2 (ja) * 1994-03-25 2001-04-09 ローム株式会社 データ転送方法及び装置
US5701433A (en) * 1994-10-14 1997-12-23 Compaq Computer Corporation Computer system having a memory controller which performs readahead operations which can be aborted prior to completion
US5598569A (en) * 1994-10-17 1997-01-28 Motorola Inc. Data processor having operating modes selected by at least one mask option bit and method therefor
US5644788A (en) * 1994-10-28 1997-07-01 Cyrix Corporation Burst transfers using an ascending or descending only burst ordering
US5787267A (en) * 1995-06-07 1998-07-28 Monolithic System Technology, Inc. Caching method and circuit for a memory system with circuit module architecture
US6470405B2 (en) * 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US5802597A (en) * 1995-12-22 1998-09-01 Cirrus Logic, Inc. SDRAM memory controller while in burst four mode supporting single data accesses
US5715476A (en) * 1995-12-29 1998-02-03 Intel Corporation Method and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logic
US6243768B1 (en) 1996-02-09 2001-06-05 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
US5926828A (en) * 1996-02-09 1999-07-20 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
US6006288A (en) * 1996-06-06 1999-12-21 Motorola, Inc. Method and apparatus for adaptable burst chip select in a data processing system
US5774135A (en) * 1996-11-05 1998-06-30 Vlsi, Technology, Inc. Non-contiguous memory location addressing scheme
US6055619A (en) * 1997-02-07 2000-04-25 Cirrus Logic, Inc. Circuits, system, and methods for processing multiple data streams
US6266379B1 (en) 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
US6457075B1 (en) * 1999-05-17 2002-09-24 Koninkijke Philips Electronics N.V. Synchronous memory system with automatic burst mode switching as a function of the selected bus master
US6611796B1 (en) * 1999-10-20 2003-08-26 Texas Instruments Incorporated Method and apparatus for combining memory blocks for in circuit emulation
US6477610B1 (en) 2000-02-04 2002-11-05 International Business Machines Corporation Reordering responses on a data bus based on size of response
US6580659B1 (en) * 2000-08-25 2003-06-17 Micron Technology, Inc. Burst read addressing in a non-volatile memory device
US6449203B1 (en) 2001-03-08 2002-09-10 Micron Technology, Inc. Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs
US6751159B2 (en) 2001-10-26 2004-06-15 Micron Technology, Inc. Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode
US6838331B2 (en) * 2002-04-09 2005-01-04 Micron Technology, Inc. Method and system for dynamically operating memory in a power-saving error correction mode
US6751143B2 (en) * 2002-04-11 2004-06-15 Micron Technology, Inc. Method and system for low power refresh of dynamic random access memories
US7149824B2 (en) 2002-07-10 2006-12-12 Micron Technology, Inc. Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction
US20130329137A1 (en) * 2011-12-28 2013-12-12 Animesh Mishra Video Encoding in Video Analytics
EP3697014A1 (de) 2019-02-16 2020-08-19 Fraunhofer Gesellschaft zur Förderung der angewandten Forschung e.V. Srs-konfiguration und -indikation für codebuch- und nicht-codebuch-basierte ul-übertragungen in einem netzwerk

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1540923A (en) * 1975-12-01 1979-02-21 Intel Corp Programmable single chip mos computer
US4249247A (en) * 1979-01-08 1981-02-03 Ncr Corporation Refresh system for dynamic RAM memory
US4286320A (en) * 1979-03-12 1981-08-25 Texas Instruments Incorporated Digital computing system having auto-incrementing memory
US4328566A (en) * 1980-06-24 1982-05-04 Pitney Bowes Inc. Dynamic memory refresh system with additional refresh cycles
JPS5898814A (ja) * 1981-12-08 1983-06-11 Sony Corp エラ−デ−タ補間装置
DE3241356A1 (de) * 1982-11-09 1984-05-10 Siemens AG, 1000 Berlin und 8000 München Vorrichtung zur mikroprogramm-steuerung eines informationstransfers und verfahren zu ihrem betrieb
JPS59140694A (ja) * 1983-01-31 1984-08-13 Sharp Corp ダイナミツクｒａｍのリフレツシユ方法
US4638451A (en) * 1983-05-03 1987-01-20 Texas Instruments Incorporated Microprocessor system with programmable interface
US4649511A (en) * 1983-07-25 1987-03-10 General Electric Company Dynamic memory controller for single-chip microprocessor
JPS60113395A (ja) * 1983-11-25 1985-06-19 Hitachi Ltd メモリ制御回路
US4742543A (en) * 1983-12-22 1988-05-03 Frederiksen Jeffrey E Video transmission system
US4694489A (en) * 1983-12-22 1987-09-15 Frederiksen Jeffrey E Video transmission system
US4800431A (en) * 1984-03-19 1989-01-24 Schlumberger Systems And Services, Inc. Video stream processing frame buffer controller
JPS60235269A (ja) * 1984-05-08 1985-11-21 Toshiba Corp デ−タ転送制御装置
US4665495A (en) * 1984-07-23 1987-05-12 Texas Instruments Incorporated Single chip dram controller and CRT controller
JPS61105143A (ja) * 1984-10-29 1986-05-23 Nec Corp バ−スト信号検出装置
US4797850A (en) * 1986-05-12 1989-01-10 Advanced Micro Devices, Inc. Dynamic random access memory controller with multiple independent control channels
JPS6329867A (ja) * 1986-07-23 1988-02-08 Nec Corp Ｄｍａコントロ−ラ
US4884234A (en) * 1987-06-29 1989-11-28 Ncr Corporation Dynamic RAM refresh circuit with DMA access
US4878197A (en) * 1987-08-17 1989-10-31 Control Data Corporation Data communication apparatus
US4870622A (en) * 1988-06-24 1989-09-26 Advanced Micro Devices, Inc. DRAM controller cache

Also Published As

Publication number Publication date
GR3020706T3 (en) 1996-11-30
EP0348113A3 (de) 1991-09-11
EP0348113B1 (de) 1996-08-14
US5134699A (en) 1992-07-28
ATE141424T1 (de) 1996-08-15
JPH0266662A (ja) 1990-03-06
EP0348113A2 (de) 1989-12-27
DE68926936D1 (de) 1996-09-19
ES2090037T3 (es) 1996-10-16
JP2992552B2 (ja) 1999-12-20

Similar Documents

Publication Publication Date Title
DE68926936T2 (de) Vorrichtung und Technik für Burstprogrammierung
JPS6436336A (en) Calculator system
DE3583044D1 (de) Tragbare vorrichtung zum speichern und verarbeiten von daten.
KR910006856A (ko) 어드레스 레지스터를 이용하여 동적으로 버스제어를 실행하는 마이크로컴퓨터
ES481636A1 (es) Un amecanismo de retencion dle control programable.
ES458222A1 (es) Perfeccionamientos introducidos en una unidad de control de dispositivo periferico con logica de escrutinio mejorada, para utilizacion en un sistema de tratamiento de datos.
DE69022644D1 (de) Steuerschaltung für den Datenausgang für eine Halbleiterspeicheranordnung.
AU1757192A (en) Apparatus and method for fast i/o transfer
JPS5730060A (en) Address space expansion system
SU1644091A1 (ru) Временное программное устройство
JPS6436339A (en) Self-diagnosis system
JPS63239544A (ja) メモリ保護回路
JPS6486262A (en) Data transferring device
JPS6418849A (en) End token output circuit
JPS5452430A (en) Address switching unit
JPS6426262A (en) 16 bit microprocessor system
JPS56114026A (en) Data processor
JPS5442943A (en) Refresh system
JPS57193850A (en) Data transfer device
JPS6419457A (en) Memory device
JPS57153352A (en) Input and output instruction tracing system
JPS6473437A (en) Memory write protection circuit
JPS6478339A (en) Address controller
JPS56127259A (en) Information processor
JPS6426960A (en) Channel device

Legal Events

Date Code Title Description
8364 No opposition during term of opposition