DE68927353T2 - Verfahren zur Herstellung einer Planarisolierung - Google Patents
Verfahren zur Herstellung einer PlanarisolierungInfo
- Publication number
- DE68927353T2 DE68927353T2 DE68927353T DE68927353T DE68927353T2 DE 68927353 T2 DE68927353 T2 DE 68927353T2 DE 68927353 T DE68927353 T DE 68927353T DE 68927353 T DE68927353 T DE 68927353T DE 68927353 T2 DE68927353 T2 DE 68927353T2
- Authority
- DE
- Germany
- Prior art keywords
- producing planar
- planar insulation
- insulation
- producing
- planar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/173,482 US4876217A (en) | 1988-03-24 | 1988-03-24 | Method of forming semiconductor structure isolation regions |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68927353D1 DE68927353D1 (de) | 1996-11-28 |
DE68927353T2 true DE68927353T2 (de) | 1997-04-24 |
Family
ID=22632228
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE68927353T Expired - Lifetime DE68927353T2 (de) | 1988-03-24 | 1989-03-20 | Verfahren zur Herstellung einer Planarisolierung |
Country Status (4)
Country | Link |
---|---|
US (1) | US4876217A (de) |
EP (1) | EP0334268B1 (de) |
JP (1) | JP3156998B2 (de) |
DE (1) | DE68927353T2 (de) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4980311A (en) * | 1987-05-05 | 1990-12-25 | Seiko Epson Corporation | Method of fabricating a semiconductor device |
US5416354A (en) * | 1989-01-06 | 1995-05-16 | Unitrode Corporation | Inverted epitaxial process semiconductor devices |
US6008107A (en) * | 1990-06-14 | 1999-12-28 | National Semiconductor Corporation | Method of planarizing integrated circuits with fully recessed isolation dielectric |
US5175123A (en) * | 1990-11-13 | 1992-12-29 | Motorola, Inc. | High-pressure polysilicon encapsulated localized oxidation of silicon |
US5290396A (en) * | 1991-06-06 | 1994-03-01 | Lsi Logic Corporation | Trench planarization techniques |
US5413966A (en) * | 1990-12-20 | 1995-05-09 | Lsi Logic Corporation | Shallow trench etch |
US5248625A (en) * | 1991-06-06 | 1993-09-28 | Lsi Logic Corporation | Techniques for forming isolation structures |
US5225358A (en) * | 1991-06-06 | 1993-07-06 | Lsi Logic Corporation | Method of forming late isolation with polishing |
US5252503A (en) * | 1991-06-06 | 1993-10-12 | Lsi Logic Corporation | Techniques for forming isolation structures |
US5604159A (en) | 1994-01-31 | 1997-02-18 | Motorola, Inc. | Method of making a contact structure |
US5385861A (en) * | 1994-03-15 | 1995-01-31 | National Semiconductor Corporation | Planarized trench and field oxide and poly isolation scheme |
US5462888A (en) * | 1994-06-06 | 1995-10-31 | At&T Ipm Corp. | Process for manufacturing semiconductor BICMOS device |
US5472913A (en) * | 1994-08-05 | 1995-12-05 | Texas Instruments Incorporated | Method of fabricating porous dielectric material with a passivation layer for electronics applications |
US6395620B1 (en) * | 1996-10-08 | 2002-05-28 | Micron Technology, Inc. | Method for forming a planar surface over low density field areas on a semiconductor wafer |
TW312821B (en) * | 1996-11-19 | 1997-08-11 | United Microelectronics Corp | Manufacturing method of shallow trench isolation |
KR100240879B1 (ko) * | 1997-05-17 | 2000-01-15 | 윤종용 | 반도체 장치의 평탄화 방법 |
US5891763A (en) * | 1997-10-22 | 1999-04-06 | Wanlass; Frank M. | Damascene pattering of SOI MOS transistors |
EP2221852B1 (de) | 1998-01-15 | 2012-05-09 | Cornell Research Foundation, Inc. | Grabenisolation für mikromechanische Bauelemente |
TW370708B (en) * | 1998-06-23 | 1999-09-21 | United Microelectronics Corp | Method for manufacturing shallow trench isolation structure without producing microscratches on surface of shallow trench isolation structure (revised edition) |
US6074931A (en) * | 1998-11-05 | 2000-06-13 | Vanguard International Semiconductor Corporation | Process for recess-free planarization of shallow trench isolation |
US6342432B1 (en) * | 1999-08-11 | 2002-01-29 | Advanced Micro Devices, Inc. | Shallow trench isolation formation without planarization mask |
US20020071169A1 (en) | 2000-02-01 | 2002-06-13 | Bowers John Edward | Micro-electro-mechanical-system (MEMS) mirror device |
US6753638B2 (en) | 2000-02-03 | 2004-06-22 | Calient Networks, Inc. | Electrostatic actuator for micromechanical systems |
US6825967B1 (en) | 2000-09-29 | 2004-11-30 | Calient Networks, Inc. | Shaped electrodes for micro-electro-mechanical-system (MEMS) devices to improve actuator performance and methods for fabricating the same |
US6544863B1 (en) | 2001-08-21 | 2003-04-08 | Calient Networks, Inc. | Method of fabricating semiconductor wafers having multiple height subsurface layers |
US6994903B2 (en) * | 2002-01-03 | 2006-02-07 | International Business Machines Corp. | Hybrid substrate and method for fabricating the same |
US7728339B1 (en) | 2002-05-03 | 2010-06-01 | Calient Networks, Inc. | Boundary isolation for microelectromechanical devices |
FR2872958B1 (fr) * | 2004-07-12 | 2008-05-02 | Commissariat Energie Atomique | Procede de fabrication d'un film mince structure et film mince obtenu par un tel procede |
DE102011012087B3 (de) * | 2011-02-23 | 2012-04-05 | Texas Instruments Deutschland Gmbh | Verfahren zur Herstellung von komplementären Bipolartransistoren |
US10636671B1 (en) * | 2019-03-08 | 2020-04-28 | United Microelectronics Corp. | Planarization process |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US32090A (en) * | 1861-04-16 | Clothes-wbiitgee | ||
US4367119A (en) * | 1980-08-18 | 1983-01-04 | International Business Machines Corporation | Planar multi-level metal process with built-in etch stop |
EP0061855B1 (de) * | 1981-03-20 | 1985-08-14 | Kabushiki Kaisha Toshiba | Verfahren zur Herstellung eines Halbleiterbauelements |
US4492717A (en) * | 1981-07-27 | 1985-01-08 | International Business Machines Corporation | Method for forming a planarized integrated circuit |
JPS5828850A (ja) * | 1981-08-12 | 1983-02-19 | Fujitsu Ltd | 半導体装置の製造方法 |
US4454647A (en) * | 1981-08-27 | 1984-06-19 | International Business Machines Corporation | Isolation for high density integrated circuits |
JPS5898943A (ja) * | 1981-12-09 | 1983-06-13 | Nec Corp | 半導体装置の製造方法 |
CA1169022A (en) * | 1982-04-19 | 1984-06-12 | Kevin Duncan | Integrated circuit planarizing process |
JPS58213444A (ja) * | 1982-06-04 | 1983-12-12 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US4446194A (en) * | 1982-06-21 | 1984-05-01 | Motorola, Inc. | Dual layer passivation |
DE3225961A1 (de) * | 1982-07-10 | 1984-01-12 | Engl, Walter L., Prof. Dr.rer.nat., 5120 Herzogenrath | Verfahren zum herstellen eines isolationsbereiches bei halbleiteranordnungen |
JPS5957449A (ja) * | 1982-09-28 | 1984-04-03 | Toshiba Corp | 半導体装置とその製造方法 |
JPS59158534A (ja) * | 1983-02-28 | 1984-09-08 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JPS59175138A (ja) * | 1983-03-23 | 1984-10-03 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPS59177941A (ja) * | 1983-03-28 | 1984-10-08 | Nec Corp | 素子分離領域の製造方法 |
JPS59217339A (ja) * | 1983-05-26 | 1984-12-07 | Toshiba Corp | 半導体装置の製造方法 |
JPS6039846A (ja) * | 1983-08-15 | 1985-03-01 | Oki Electric Ind Co Ltd | 半導体集積回路装置の製造方法 |
JPS6050939A (ja) * | 1983-08-30 | 1985-03-22 | Toshiba Corp | 半導体装置の製造方法 |
JPS60132341A (ja) * | 1983-12-21 | 1985-07-15 | Hitachi Ltd | 半導体装置 |
JPS60142535A (ja) * | 1983-12-28 | 1985-07-27 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JPS60236244A (ja) * | 1984-05-09 | 1985-11-25 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US4589193A (en) * | 1984-06-29 | 1986-05-20 | International Business Machines Corporation | Metal silicide channel stoppers for integrated circuits and method for making the same |
JPS6155939A (ja) * | 1984-08-28 | 1986-03-20 | Toshiba Corp | 半導体装置の製造方法 |
US4571819A (en) * | 1984-11-01 | 1986-02-25 | Ncr Corporation | Method for forming trench isolation structures |
US4665010A (en) * | 1985-04-29 | 1987-05-12 | International Business Machines Corporation | Method of fabricating photopolymer isolation trenches in the surface of a semiconductor wafer |
US4662986A (en) * | 1985-06-27 | 1987-05-05 | Signetics Corporation | Planarization method and technique for isolating semiconductor islands |
US4662064A (en) * | 1985-08-05 | 1987-05-05 | Rca Corporation | Method of forming multi-level metallization |
US4704368A (en) * | 1985-10-30 | 1987-11-03 | International Business Machines Corporation | Method of making trench-incorporated monolithic semiconductor capacitor and high density dynamic memory cells including the capacitor |
US4689113A (en) * | 1986-03-21 | 1987-08-25 | International Business Machines Corporation | Process for forming planar chip-level wiring |
US4676868A (en) * | 1986-04-23 | 1987-06-30 | Fairchild Semiconductor Corporation | Method for planarizing semiconductor substrates |
US4676867A (en) * | 1986-06-06 | 1987-06-30 | Rockwell International Corporation | Planarization process for double metal MOS using spin-on glass as a sacrificial layer |
-
1988
- 1988-03-24 US US07/173,482 patent/US4876217A/en not_active Expired - Lifetime
-
1989
- 1989-03-20 DE DE68927353T patent/DE68927353T2/de not_active Expired - Lifetime
- 1989-03-20 EP EP89104972A patent/EP0334268B1/de not_active Expired - Lifetime
- 1989-03-22 JP JP06775989A patent/JP3156998B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US4876217A (en) | 1989-10-24 |
JPH01276641A (ja) | 1989-11-07 |
EP0334268A3 (de) | 1991-01-30 |
EP0334268B1 (de) | 1996-10-23 |
DE68927353D1 (de) | 1996-11-28 |
EP0334268A2 (de) | 1989-09-27 |
JP3156998B2 (ja) | 2001-04-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE68927353T2 (de) | Verfahren zur Herstellung einer Planarisolierung | |
DE69119587D1 (de) | Verfahren zur herstellung von tagatose | |
DE69110452T2 (de) | Verfahren zur Herstellung einer Isolierung. | |
DE3689164D1 (de) | Verfahren zur Herstellung einer elastischen Form. | |
ATA53886A (de) | Verfahren zur herstellung von chlordioxid | |
DE69031222T2 (de) | Verfahren zur herstellung einer 3-substituierten thio-3-cephemverbindung | |
DE69313799D1 (de) | Verfahren zur Herstellung von Schneidklemmkontakten | |
DE69033758T2 (de) | Verfahren zur herstellung von norcamphandikarbonitrilen | |
ATA903089A (de) | Verfahren zur herstellung formbeständiger gegenstände | |
DE69404201D1 (de) | Verfahren zur Herstellung einer Isolationsplatte | |
ATA95587A (de) | Verfahren zur herstellung von glucosylmoranolin | |
AT379414B (de) | Verfahren zur herstellung von mehrschichtlackierungen | |
DE3683373D1 (de) | Verfahren zur herstellung emulgierbarer polyethylen-paraffin-mischzubereitungen. | |
ATA206287A (de) | Verfahren zur herstellung einer backware | |
ATA88387A (de) | Verfahren zur herstellung des tripeptids arg-ala-arg | |
ATA178085A (de) | Verfahren zur herstellung von 1-thiosubstituierten n-methyl-2-nitroaethenaminen | |
ATA166787A (de) | Verfahren zur herstellung einer zum isolieren gegen feuchtigkeit geeigneten komposition | |
ATA252985A (de) | Verfahren zur herstellung von | |
ATA121387A (de) | Verfahren zur herstellung von moranolinderivaten | |
DE59006754D1 (de) | Verfahren zur Herstellung einer Hochtemperatursuperisolation. | |
AT397651B (de) | Verfahren zur herstellung von bromfluormethan | |
AT389510B (de) | Verfahren zur herstellung von 2-guanidinothiazol- derivaten | |
ATA8987A (de) | Verfahren zur herstellung von alkylaminoethylaminoethylglycinen | |
ATA217289A (de) | Verfahren zur herstellung von pizzen | |
ATA119884A (de) | Verfahren zur herstellung von cephalosporinantibiotika |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: FREESCALE SEMICONDUCTOR, INC. (N.D.GES.D. STAATES |