DE68927552D1 - Speichervorrichtungen - Google Patents

Speichervorrichtungen

Info

Publication number
DE68927552D1
DE68927552D1 DE68927552T DE68927552T DE68927552D1 DE 68927552 D1 DE68927552 D1 DE 68927552D1 DE 68927552 T DE68927552 T DE 68927552T DE 68927552 T DE68927552 T DE 68927552T DE 68927552 D1 DE68927552 D1 DE 68927552D1
Authority
DE
Germany
Prior art keywords
storage devices
devices
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68927552T
Other languages
English (en)
Other versions
DE68927552T2 (de
Inventor
Fumio Miyaji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63036712A external-priority patent/JPH01211394A/ja
Priority claimed from JP63036711A external-priority patent/JPH01212114A/ja
Priority claimed from JP63037908A external-priority patent/JPH01213890A/ja
Application filed by Sony Corp filed Critical Sony Corp
Publication of DE68927552D1 publication Critical patent/DE68927552D1/de
Application granted granted Critical
Publication of DE68927552T2 publication Critical patent/DE68927552T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
DE68927552T 1988-02-19 1989-02-20 Speichervorrichtungen Expired - Fee Related DE68927552T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP63036712A JPH01211394A (ja) 1988-02-19 1988-02-19 メモリ装置
JP63036711A JPH01212114A (ja) 1988-02-19 1988-02-19 パルス発生回路
JP63037908A JPH01213890A (ja) 1988-02-20 1988-02-20 メモリ装置

Publications (2)

Publication Number Publication Date
DE68927552D1 true DE68927552D1 (de) 1997-01-23
DE68927552T2 DE68927552T2 (de) 1997-04-10

Family

ID=27289191

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68927552T Expired - Fee Related DE68927552T2 (de) 1988-02-19 1989-02-20 Speichervorrichtungen

Country Status (3)

Country Link
US (2) US5054000A (de)
EP (2) EP0331322A3 (de)
DE (1) DE68927552T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5255225A (en) * 1989-04-05 1993-10-19 Hitachi, Ltd. Semiconductor integrated circuit device and memory consisting of semiconductor integrated circuit
JP2825291B2 (ja) * 1989-11-13 1998-11-18 株式会社東芝 半導体記憶装置
DE69024921T2 (de) * 1989-11-24 1996-09-05 Nec Corp Halbleiterspeicheranordnung mit rückstellbaren Speicherzellen
JP2740063B2 (ja) * 1990-10-15 1998-04-15 株式会社東芝 半導体記憶装置
US6249481B1 (en) 1991-10-15 2001-06-19 Kabushiki Kaisha Toshiba Semiconductor memory device
US5228106A (en) * 1991-05-30 1993-07-13 Integrated Device Technology, Inc. Track-and-regenerate amplifiers and memories using such amplifiers
WO1992022070A1 (en) * 1991-05-30 1992-12-10 Integrated Device Technology, Inc. Static memories and methods of reading static memories
JP2970253B2 (ja) * 1991-10-04 1999-11-02 住友金属工業株式会社 半導体装置及びその製造方法
JPH05166368A (ja) * 1991-12-18 1993-07-02 Sharp Corp 擬似ｓｒａｍ
US6310821B1 (en) * 1998-07-10 2001-10-30 Kabushiki Kaisha Toshiba Clock-synchronous semiconductor memory device and access method thereof
DE69325119T2 (de) * 1992-03-19 1999-11-04 Toshiba Kawasaki Kk Taktsynchronisierter Halbleiterspeicheranordnung und Zugriffsverfahren
US5267213A (en) * 1992-03-31 1993-11-30 Intel Corporation Bias circuitry for content addressable memory cells of a floating gate nonvolatile memory
US5537350A (en) * 1993-09-10 1996-07-16 Intel Corporation Method and apparatus for sequential programming of the bits in a word of a flash EEPROM memory array
US5493537A (en) * 1994-02-28 1996-02-20 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with edge transition detection pulse disable
US5572473A (en) * 1994-11-29 1996-11-05 Sony Corporation Of Japan Bit line conditioning circuit for random access memory
US5566121A (en) * 1995-08-30 1996-10-15 International Business Machines Corporation Method for PCMCIA card function using DRAM technology
DE19612440C1 (de) * 1996-03-28 1997-05-07 Siemens Ag Schaltungsanordnung mit einer Anzahl von elektronischen Schaltungskomponenten
FR2760286B1 (fr) * 1997-02-28 1999-04-16 Sgs Thomson Microelectronics Procede d'effacement d'une memoire ram statique et memoire en circuit integre associe
US6301147B1 (en) 1997-12-17 2001-10-09 National Scientific Corporation Electronic semiconductor circuit which includes a tunnel diode
US6990011B2 (en) * 2003-05-09 2006-01-24 Stmicroelectronics, Inc. Memory circuit and method for corrupting stored data
US7224600B2 (en) * 2004-01-08 2007-05-29 Stmicroelectronics, Inc. Tamper memory cell
US7057427B2 (en) * 2004-07-15 2006-06-06 Freescale Semiconductor, Inc Power on reset circuit
US8351287B1 (en) * 2010-12-22 2013-01-08 Lattice Semiconductor Corporation Bitline floating circuit for memory power reduction
KR20160006482A (ko) * 2014-07-09 2016-01-19 에스케이하이닉스 주식회사 반도체 장치
CN111736679B (zh) * 2020-06-24 2022-08-05 广东安居宝数码科技股份有限公司 芯片复位方法、装置和单片机

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US467578A (en) * 1892-01-26 And john j
US3852724A (en) * 1973-03-30 1974-12-03 Texas Instruments Inc Surface wave clock and serial data storage unit
JPS5827915B2 (ja) * 1978-07-28 1983-06-13 富士通株式会社 リセット回路
US4229666A (en) * 1978-09-27 1980-10-21 Gte Products Corporation Audio detector circuit
JPS5781665A (en) * 1980-11-07 1982-05-21 Toshiba Corp Single-chip microcomputer
JPS58222489A (ja) * 1982-06-18 1983-12-24 Nec Corp 半導体記憶装置
US4567578A (en) * 1982-09-08 1986-01-28 Harris Corporation Cache memory flush scheme
US4587629A (en) * 1983-12-30 1986-05-06 International Business Machines Corporation Random address memory with fast clear
US4758993A (en) * 1984-11-19 1988-07-19 Fujitsu Limited Random access memory device formed on a semiconductor substrate having an array of memory cells divided into sub-arrays
EP0189700A3 (de) * 1984-12-28 1988-04-27 Thomson Components-Mostek Corporation Statischer Speicher mit schnellem Nullsetzen
US4627031A (en) * 1985-01-07 1986-12-02 Thomson Components-Mostek Corporation CMOS memory arrangement
US4716323A (en) * 1985-04-27 1987-12-29 Kabushiki Kaisha Toshiba Power voltage drop detecting circuit
JPH0640439B2 (ja) * 1986-02-17 1994-05-25 日本電気株式会社 半導体記憶装置
JPS6383991A (ja) * 1986-09-29 1988-04-14 Toshiba Corp スタテイツク型メモリ
JPH01130385A (ja) * 1987-11-17 1989-05-23 Sony Corp メモリ装置
US4949309A (en) * 1988-05-11 1990-08-14 Catalyst Semiconductor, Inc. EEPROM utilizing single transistor per cell capable of both byte erase and flash erase
KR940008717B1 (ko) * 1989-03-06 1994-09-26 마쯔시다덴기산교 가부시기가이샤 다이내믹 ram의 판독회로

Also Published As

Publication number Publication date
EP0331322A3 (de) 1991-06-12
EP0574094A3 (en) 1994-07-20
DE68927552T2 (de) 1997-04-10
EP0574094B1 (de) 1996-12-11
EP0331322A2 (de) 1989-09-06
US5047985A (en) 1991-09-10
EP0574094A2 (de) 1993-12-15
US5054000A (en) 1991-10-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee