DE68928343T2 - Schreib-Lese/Schreib-Weitergabe-Speichersubsystemzyklus - Google Patents
Schreib-Lese/Schreib-Weitergabe-SpeichersubsystemzyklusInfo
- Publication number
- DE68928343T2 DE68928343T2 DE68928343T DE68928343T DE68928343T2 DE 68928343 T2 DE68928343 T2 DE 68928343T2 DE 68928343 T DE68928343 T DE 68928343T DE 68928343 T DE68928343 T DE 68928343T DE 68928343 T2 DE68928343 T2 DE 68928343T2
- Authority
- DE
- Germany
- Prior art keywords
- data
- write
- cpu
- current
- scu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/302,839 US5185875A (en) | 1989-01-27 | 1989-01-27 | Method and apparatus for reducing memory read latency in a shared memory system with multiple processors |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68928343D1 DE68928343D1 (de) | 1997-10-30 |
DE68928343T2 true DE68928343T2 (de) | 1998-05-07 |
Family
ID=23169428
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE68928343T Expired - Fee Related DE68928343T2 (de) | 1989-01-27 | 1989-07-03 | Schreib-Lese/Schreib-Weitergabe-Speichersubsystemzyklus |
Country Status (6)
Country | Link |
---|---|
US (1) | US5185875A (de) |
EP (1) | EP0379769B1 (de) |
JP (1) | JPH0642230B2 (de) |
AT (1) | ATE158661T1 (de) |
CA (1) | CA1323446C (de) |
DE (1) | DE68928343T2 (de) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5371874A (en) * | 1989-01-27 | 1994-12-06 | Digital Equipment Corporation | Write-read/write-pass memory subsystem cycle |
US5287512A (en) * | 1990-08-06 | 1994-02-15 | Ncr Corporation | Computer memory system and method for cleaning data elements |
US5420994A (en) * | 1990-08-06 | 1995-05-30 | Ncr Corp. | Method for reading a multiple byte data element in a memory system with at least one cache and a main memory |
EP0475730B1 (de) * | 1990-09-14 | 1997-12-10 | Digital Equipment Corporation | Schreib-Lese/Schreib-Weitergabe-Zyklus für Speicheruntersystem |
JPH0827755B2 (ja) * | 1991-02-15 | 1996-03-21 | インターナショナル・ビジネス・マシーンズ・コーポレイション | データの単位を高速度でアクセスする方法 |
US5530835A (en) * | 1991-09-18 | 1996-06-25 | Ncr Corporation | Computer memory data merging technique for computers with write-back caches |
US5491811A (en) * | 1992-04-20 | 1996-02-13 | International Business Machines Corporation | Cache system using mask bits to recorder the sequences for transfers of data through cache to system memory |
JP3309425B2 (ja) * | 1992-05-22 | 2002-07-29 | 松下電器産業株式会社 | キャッシュ制御装置 |
US5862358A (en) * | 1994-12-20 | 1999-01-19 | Digital Equipment Corporation | Method and apparatus for reducing the apparent read latency when connecting busses with fixed read reply timeouts to CPUs with write-back caches |
US5829052A (en) * | 1994-12-28 | 1998-10-27 | Intel Corporation | Method and apparatus for managing memory accesses in a multiple multiprocessor cluster system |
JPH08314794A (ja) * | 1995-02-28 | 1996-11-29 | Matsushita Electric Ind Co Ltd | 安定記憶装置へのアクセス待ち時間を短縮するための方法およびシステム |
US5625778A (en) * | 1995-05-03 | 1997-04-29 | Apple Computer, Inc. | Method and apparatus for presenting an access request from a computer system bus to a system resource with reduced latency |
US5867642A (en) * | 1995-08-10 | 1999-02-02 | Dell Usa, L.P. | System and method to coherently and dynamically remap an at-risk memory area by simultaneously writing two memory areas |
JP2814988B2 (ja) * | 1996-04-12 | 1998-10-27 | 日本電気株式会社 | 障害処理方式 |
US6098115A (en) * | 1998-04-08 | 2000-08-01 | International Business Machines Corporation | System for reducing storage access latency with accessing main storage and data bus simultaneously |
US6401175B1 (en) * | 1999-10-01 | 2002-06-04 | Sun Microsystems, Inc. | Shared write buffer for use by multiple processor units |
US7099997B2 (en) * | 2003-02-27 | 2006-08-29 | International Business Machines Corporation | Read-modify-write avoidance using a boundary word storage mechanism |
US7320063B1 (en) * | 2005-02-04 | 2008-01-15 | Sun Microsystems, Inc. | Synchronization primitives for flexible scheduling of functional unit operations |
US9037670B2 (en) * | 2012-09-18 | 2015-05-19 | Cisco Technology, Inc. | Ultra low latency network buffer storage |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3771137A (en) * | 1971-09-10 | 1973-11-06 | Ibm | Memory control in a multipurpose system utilizing a broadcast |
FR129151A (de) * | 1974-02-09 | |||
US4142234A (en) * | 1977-11-28 | 1979-02-27 | International Business Machines Corporation | Bias filter memory for filtering out unnecessary interrogations of cache directories in a multiprocessor system |
US4228503A (en) * | 1978-10-02 | 1980-10-14 | Sperry Corporation | Multiplexed directory for dedicated cache memory system |
JPS55134459A (en) * | 1979-04-06 | 1980-10-20 | Hitachi Ltd | Data processing system |
US4410944A (en) * | 1981-03-24 | 1983-10-18 | Burroughs Corporation | Apparatus and method for maintaining cache memory integrity in a shared memory environment |
US4503497A (en) * | 1982-05-27 | 1985-03-05 | International Business Machines Corporation | System for independent cache-to-cache transfer |
US4695951A (en) * | 1983-07-07 | 1987-09-22 | Honeywell Bull Inc. | Computer hierarchy control |
US4747043A (en) * | 1984-02-10 | 1988-05-24 | Prime Computer, Inc. | Multiprocessor cache coherence system |
US4663742A (en) * | 1984-10-30 | 1987-05-05 | International Business Machines Corporation | Directory memory system having simultaneous write, compare and bypass capabilites |
US4847804A (en) * | 1985-02-05 | 1989-07-11 | Digital Equipment Corporation | Apparatus and method for data copy consistency in a multi-cache data processing unit |
US4755930A (en) * | 1985-06-27 | 1988-07-05 | Encore Computer Corporation | Hierarchical cache memory system and method |
US5018063A (en) * | 1988-12-05 | 1991-05-21 | International Business Machines Corporation | Method for reducing cross-interrogate delays in a multiprocessor system |
-
1989
- 1989-01-27 US US07/302,839 patent/US5185875A/en not_active Expired - Lifetime
- 1989-06-12 CA CA000602465A patent/CA1323446C/en not_active Expired - Fee Related
- 1989-06-28 JP JP1166501A patent/JPH0642230B2/ja not_active Expired - Lifetime
- 1989-07-03 AT AT89306720T patent/ATE158661T1/de not_active IP Right Cessation
- 1989-07-03 EP EP89306720A patent/EP0379769B1/de not_active Expired - Lifetime
- 1989-07-03 DE DE68928343T patent/DE68928343T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0379769A3 (de) | 1991-06-19 |
US5185875A (en) | 1993-02-09 |
DE68928343D1 (de) | 1997-10-30 |
JPH0642230B2 (ja) | 1994-06-01 |
JPH02205964A (ja) | 1990-08-15 |
ATE158661T1 (de) | 1997-10-15 |
CA1323446C (en) | 1993-10-19 |
EP0379769B1 (de) | 1997-09-24 |
EP0379769A2 (de) | 1990-08-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE68928343T2 (de) | Schreib-Lese/Schreib-Weitergabe-Speichersubsystemzyklus | |
EP0777184B1 (de) | Cachespeicherkohärenzverfahren und-system | |
DE3782335D1 (de) | Speichersteuersystem. | |
DE60008088D1 (de) | Mehrprozessorsystem Prüfungsschaltung | |
DE69425222D1 (de) | Dynamisch ausbaubares Speichereinheitsmatrixsystem | |
DE3743515A1 (de) | Hochleistungs-mikroprozessor | |
KR100515059B1 (ko) | 멀티프로세서 시스템 및 멀티프로세서 시스템의 캐쉬일관성 유지 방법 | |
JPH04233046A (ja) | メモリモジュール用のアドレスをイネーブルする方法及びその装置 | |
TW343305B (en) | Cache control system | |
DE3782500D1 (de) | Gemeinsam genutzte speicherschnittstelle fuer datenverarbeitungsanlage. | |
EP0293720A3 (de) | Durchsichtiger Cache-Speicher | |
EP0379771A3 (de) | Leseabbruchverfahren | |
US6601145B2 (en) | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls | |
JP2001306265A5 (de) | ||
JPH0319976B2 (de) | ||
JPS6476346A (en) | Disk cache control system | |
JP3013631B2 (ja) | キャッシュメモリ同期方法 | |
ATE208926T1 (de) | Adaptive speichersteureinrichtung für ein symmetrisches mehrprozessorsystem | |
JPS55108027A (en) | Processor system | |
US6546468B2 (en) | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers performing directory update | |
US20230367712A1 (en) | Tracking memory modifications at cache line granularity | |
KR940703050A (ko) | 다중 기록 캐쉬를 포함한 메모리 유닛(memory unit including a multiple write cache) | |
US20020129209A1 (en) | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers | |
EP0396940A3 (de) | Cache-Speicher und verwandtes Übereinstimmungsprotokoll | |
JPS59135684A (ja) | バツフアメモリ間のデ−タバイパス方式 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |