DE68928374D1 - Datenprozessor mit Null-Ausführungszyklus für einen bedingten Sprung-Befehl - Google Patents

Datenprozessor mit Null-Ausführungszyklus für einen bedingten Sprung-Befehl

Info

Publication number
DE68928374D1
DE68928374D1 DE68928374T DE68928374T DE68928374D1 DE 68928374 D1 DE68928374 D1 DE 68928374D1 DE 68928374 T DE68928374 T DE 68928374T DE 68928374 T DE68928374 T DE 68928374T DE 68928374 D1 DE68928374 D1 DE 68928374D1
Authority
DE
Germany
Prior art keywords
data processor
jump instruction
execution cycle
conditional jump
zero execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68928374T
Other languages
English (en)
Other versions
DE68928374T2 (de
Inventor
Masato Suzuki
Masashi Deguchi
Yukinobu Nishikawa
Toshimichi Matsuzaki
Masaya Miyazaki
Takashi Sakao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE68928374D1 publication Critical patent/DE68928374D1/de
Publication of DE68928374T2 publication Critical patent/DE68928374T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
DE68928374T 1988-12-21 1989-12-19 Datenprozessor mit Null-Ausführungszyklus für einen bedingten Sprung-Befehl Expired - Lifetime DE68928374T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63322631A JPH0769811B2 (ja) 1988-12-21 1988-12-21 データ処理装置

Publications (2)

Publication Number Publication Date
DE68928374D1 true DE68928374D1 (de) 1997-11-13
DE68928374T2 DE68928374T2 (de) 1998-03-19

Family

ID=18145869

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68928374T Expired - Lifetime DE68928374T2 (de) 1988-12-21 1989-12-19 Datenprozessor mit Null-Ausführungszyklus für einen bedingten Sprung-Befehl

Country Status (5)

Country Link
US (1) US5237666A (de)
EP (1) EP0375364B1 (de)
JP (1) JPH0769811B2 (de)
KR (1) KR920006744B1 (de)
DE (1) DE68928374T2 (de)

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US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
US5230068A (en) * 1990-02-26 1993-07-20 Nexgen Microsystems Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
US5303356A (en) * 1990-05-04 1994-04-12 International Business Machines Corporation System for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tag
JPH0460720A (ja) * 1990-06-29 1992-02-26 Hitachi Ltd 条件分岐命令制御方式
US5287467A (en) * 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
JP3182438B2 (ja) * 1991-10-28 2001-07-03 株式会社日立製作所 データプロセッサ
US5434986A (en) * 1992-01-09 1995-07-18 Unisys Corporation Interdependency control of pipelined instruction processor using comparing result of two index registers of skip instruction and next sequential instruction
JP2761688B2 (ja) * 1992-02-07 1998-06-04 三菱電機株式会社 データ処理装置
US5507028A (en) * 1992-03-30 1996-04-09 International Business Machines Corporation History based branch prediction accessed via a history based earlier instruction address
DE69311330T2 (de) 1992-03-31 1997-09-25 Seiko Epson Corp Befehlsablauffolgeplanung von einem risc-superskalarprozessor
WO1993022722A1 (en) 1992-05-01 1993-11-11 Seiko Epson Corporation A system and method for retiring instructions in a superscalar microprocessor
US5784604A (en) * 1992-10-09 1998-07-21 International Business Machines Corporation Method and system for reduced run-time delay during conditional branch execution in pipelined processor systems utilizing selectively delayed sequential instruction purging
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
JP3531166B2 (ja) 1992-12-31 2004-05-24 セイコーエプソン株式会社 レジスタ・リネーミングのシステム及び方法
US5577217A (en) * 1993-05-14 1996-11-19 Intel Corporation Method and apparatus for a branch target buffer with shared branch pattern tables for associated branch predictions
GB2285154B (en) * 1993-12-24 1998-04-01 Advanced Risc Mach Ltd Branch cache
US5666505A (en) * 1994-03-11 1997-09-09 Advanced Micro Devices, Inc. Heuristic prefetch mechanism and method for computer system
US5790845A (en) * 1995-02-24 1998-08-04 Hitachi, Ltd. System with reservation instruction execution to store branch target address for use upon reaching the branch point
US6052801A (en) * 1995-05-10 2000-04-18 Intel Corporation Method and apparatus for providing breakpoints on a selectable address range
US5659679A (en) * 1995-05-30 1997-08-19 Intel Corporation Method and apparatus for providing breakpoints on taken jumps and for providing software profiling in a computer system
US5740413A (en) * 1995-06-19 1998-04-14 Intel Corporation Method and apparatus for providing address breakpoints, branch breakpoints, and single stepping
US5621886A (en) * 1995-06-19 1997-04-15 Intel Corporation Method and apparatus for providing efficient software debugging
US5694568A (en) * 1995-07-27 1997-12-02 Board Of Trustees Of The University Of Illinois Prefetch system applicable to complex memory access schemes
US5742805A (en) * 1996-02-15 1998-04-21 Fujitsu Ltd. Method and apparatus for a single history register based branch predictor in a superscalar microprocessor
US5919256A (en) * 1996-03-26 1999-07-06 Advanced Micro Devices, Inc. Operand cache addressed by the instruction address for reducing latency of read instruction
US5991874A (en) * 1996-06-06 1999-11-23 Intel Corporation Conditional move using a compare instruction generating a condition field
US5867699A (en) * 1996-07-25 1999-02-02 Unisys Corporation Instruction flow control for an instruction processor
US6427192B1 (en) * 1998-09-21 2002-07-30 Advanced Micro Devices, Inc. Method and apparatus for caching victimized branch predictions
JP4060506B2 (ja) * 1999-12-28 2008-03-12 株式会社東芝 ディスク制御装置
US6965983B2 (en) * 2003-02-16 2005-11-15 Faraday Technology Corp. Simultaneously setting prefetch address and fetch address pipelined stages upon branch
ATE491986T1 (de) * 2003-07-09 2011-01-15 Nxp Bv Verfahren und system zur zweigprädiktion
US7234046B2 (en) * 2004-12-01 2007-06-19 Faraday Technology Corp. Branch prediction using precedent instruction address of relative offset determined based on branch type and enabling skipping
US20070294518A1 (en) * 2006-06-14 2007-12-20 Shen-Chang Wang System and method for predicting target address of branch instruction utilizing branch target buffer having entry indexed according to program counter value of previous instruction
US9069547B2 (en) 2006-09-22 2015-06-30 Intel Corporation Instruction and logic for processing text strings
GB2458295B (en) * 2008-03-12 2012-01-11 Advanced Risc Mach Ltd Cache accessing using a micro tag
US9654483B1 (en) * 2014-12-23 2017-05-16 Amazon Technologies, Inc. Network communication rate limiter
US9438412B2 (en) * 2014-12-23 2016-09-06 Palo Alto Research Center Incorporated Computer-implemented system and method for multi-party data function computing using discriminative dimensionality-reducing mappings
US9569613B2 (en) * 2014-12-23 2017-02-14 Intel Corporation Techniques for enforcing control flow integrity using binary translation
US10664280B2 (en) * 2015-11-09 2020-05-26 MIPS Tech, LLC Fetch ahead branch target buffer

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Publication number Priority date Publication date Assignee Title
US4062058A (en) * 1976-02-13 1977-12-06 The United States Of America As Represented By The Secretary Of The Navy Next address subprocessor
JPS5860355A (ja) * 1981-10-07 1983-04-09 Nec Corp 情報処理装置
JPS58123141A (ja) * 1982-01-19 1983-07-22 Nec Corp 高速計数分岐実行方式
DE3382350D1 (de) * 1982-11-17 1991-08-29 Nec Corp Anordnung zum vorabholen von befehlen mit vorhersage einer verzweigungszieladresse.
JP2508021B2 (ja) * 1986-10-01 1996-06-19 三菱電機株式会社 デ−タ処理装置
JP2603626B2 (ja) * 1987-01-16 1997-04-23 三菱電機株式会社 データ処理装置
GB8728493D0 (en) * 1987-12-05 1988-01-13 Int Computers Ltd Jump prediction

Also Published As

Publication number Publication date
DE68928374T2 (de) 1998-03-19
EP0375364B1 (de) 1997-10-08
JPH02166520A (ja) 1990-06-27
KR900010553A (ko) 1990-07-07
EP0375364A2 (de) 1990-06-27
EP0375364A3 (de) 1992-06-10
JPH0769811B2 (ja) 1995-07-31
KR920006744B1 (ko) 1992-08-17
US5237666A (en) 1993-08-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP