US6522985B1
(en)
*
|
1989-07-31 |
2003-02-18 |
Texas Instruments Incorporated |
Emulation devices, systems and methods utilizing state machines
|
JP3005250B2
(ja)
*
|
1989-06-30 |
2000-01-31 |
テキサス インスツルメンツ インコーポレイテツド |
バスモニター集積回路
|
JP2820975B2
(ja)
*
|
1989-09-20 |
1998-11-05 |
富士通株式会社 |
大規模集積回路のスキャンテスト方法
|
FR2665593A1
(fr)
*
|
1990-08-03 |
1992-02-07 |
Alcatel Radiotelephone |
Circuit integre comprenant une cellule standard, une cellule d'application et une cellule de test.
|
US5498972A
(en)
*
|
1990-08-15 |
1996-03-12 |
Telefonaktiebolaget Lm Ericsson |
Device for monitoring the supply voltage on integrated circuits
|
SE466875B
(sv)
*
|
1990-08-15 |
1992-04-13 |
Ellemtel Utvecklings Ab |
Anordning foer att oevervaka matningsspaenningen lokalt paa integrerad krets
|
US5130988A
(en)
*
|
1990-09-17 |
1992-07-14 |
Northern Telecom Limited |
Software verification by fault insertion
|
FR2666902B1
(fr)
*
|
1990-09-18 |
1993-01-22 |
Thomson Composants Militaires |
Circuit integre avec registre de test peripherique.
|
EP0487941A3
(en)
*
|
1990-11-30 |
1992-08-05 |
Siemens Aktiengesellschaft |
Testable integrated circuit and associated circuitry
|
WO1992011617A1
(fr)
*
|
1990-12-19 |
1992-07-09 |
Patrick Macron |
Dispositif de protection contre le vol notamment d'un vehicule automobile
|
DE69220522T2
(de)
*
|
1991-03-13 |
1997-12-18 |
Ncr Int Inc |
Bidirektionaler Boundary-Scan-Schaltkreis
|
US5260948A
(en)
*
|
1991-03-13 |
1993-11-09 |
Ncr Corporation |
Bidirectional boundary-scan circuit
|
GB9111179D0
(en)
*
|
1991-05-23 |
1991-07-17 |
Motorola Gmbh |
An implementation of the ieee 1149.1 boundary-scan architecture
|
AU649476B2
(en)
*
|
1991-09-18 |
1994-05-26 |
Alcatel N.V. |
Integrated circuit comprising a standard cell, an application cell and a test cell
|
US5448166A
(en)
*
|
1992-01-03 |
1995-09-05 |
Hewlett-Packard Company |
Powered testing of mixed conventional/boundary-scan logic
|
US5260649A
(en)
*
|
1992-01-03 |
1993-11-09 |
Hewlett-Packard Company |
Powered testing of mixed conventional/boundary-scan logic
|
DE4225204C2
(de)
*
|
1992-06-30 |
1994-07-14 |
Siemens Ag |
Schieberegisterzelle einer Prüfschaltung zur Implementierung einer taktgesteuerten Schieberegisterprüfarchitektur(Boundary-Scan)
|
DE4318422A1
(de)
*
|
1993-06-03 |
1994-12-08 |
Philips Patentverwaltung |
Integrierte Schaltung mit Registerstufen
|
JP2727930B2
(ja)
*
|
1993-10-04 |
1998-03-18 |
日本電気株式会社 |
バウンダリスキャンテスト回路
|
FR2716019B1
(fr)
*
|
1994-02-04 |
1996-04-26 |
Sgs Thomson Microelectronics |
Circuit de traitement numérique comportant des registres de test.
|
US5715254A
(en)
*
|
1994-11-21 |
1998-02-03 |
Texas Instruments Incorporated |
Very low overhead shared resource boundary scan design
|
SE504041C2
(sv)
*
|
1995-03-16 |
1996-10-21 |
Ericsson Telefon Ab L M |
Integrerat kretsarrangemang för provning
|
US5719879A
(en)
*
|
1995-12-21 |
1998-02-17 |
International Business Machines Corporation |
Scan-bypass architecture without additional external latches
|
US5859657A
(en)
*
|
1995-12-28 |
1999-01-12 |
Eastman Kodak Company |
Led printhead and driver chip for use therewith having boundary scan test architecture
|
US5648973A
(en)
*
|
1996-02-06 |
1997-07-15 |
Ast Research, Inc. |
I/O toggle test method using JTAG
|
US6282506B1
(en)
*
|
1996-02-20 |
2001-08-28 |
Matsushita Electric Industrial Co., Ltd. |
Method of designing semiconductor integrated circuit
|
US5907562A
(en)
*
|
1996-07-31 |
1999-05-25 |
Nokia Mobile Phones Limited |
Testable integrated circuit with reduced power dissipation
|
JP3614993B2
(ja)
*
|
1996-09-03 |
2005-01-26 |
株式会社ルネサステクノロジ |
テスト回路
|
US5715256A
(en)
*
|
1996-09-27 |
1998-02-03 |
Sun Microsystems, Inc. |
Method and apparatus for handling multiplexer contention during scan
|
US5968192A
(en)
*
|
1997-05-09 |
1999-10-19 |
Artisan Components, Inc. |
Programmable universal test interface and method for making the same
|
US6006347A
(en)
*
|
1997-09-17 |
1999-12-21 |
Cypress Semiconductor Corporation |
Test mode features for synchronous pipelined memories
|
US5953285A
(en)
*
|
1997-09-17 |
1999-09-14 |
Cypress Semiconductor Corp. |
Scan path circuitry including an output register having a flow through mode
|
KR100504688B1
(ko)
*
|
1997-11-15 |
2005-10-12 |
삼성전자주식회사 |
반도체칩테스트회로
|
US6070259A
(en)
*
|
1998-01-15 |
2000-05-30 |
Lsi Logic Corporation |
Dynamic logic element having non-invasive scan chain insertion
|
US7155646B2
(en)
*
|
1999-02-10 |
2006-12-26 |
Texas Instruments Incorporated |
Tap and test controller with separate enable inputs
|
US6185710B1
(en)
|
1998-03-30 |
2001-02-06 |
International Business Machines Corporation |
High-performance IEEE1149.1-compliant boundary scan cell
|
US5968196A
(en)
*
|
1998-04-21 |
1999-10-19 |
Atmel Corporation |
Configuration control in a programmable logic device using non-volatile elements
|
DE69933349T2
(de)
*
|
1998-04-23 |
2007-05-03 |
Koninklijke Philips Electronics N.V. |
Prüfbares ic mit analogen und digitalen schaltungen
|
JPH11328972A
(ja)
*
|
1998-05-18 |
1999-11-30 |
Mitsubishi Electric Corp |
半導体装置、その設計方法およびその検査方法
|
US6182256B1
(en)
*
|
1998-06-16 |
2001-01-30 |
National Semiconductor Corporation |
Scan flip-flop that simultaneously holds logic values from a serial load and a subsequent parallel load
|
US6446230B1
(en)
|
1998-09-14 |
2002-09-03 |
Cisco Technology, Inc. |
Mechanism for enabling compliance with the IEEE standard 1149.1 for boundary-scan designs and tests
|
US6266801B1
(en)
*
|
1998-09-15 |
2001-07-24 |
Adaptec, Inc. |
Boundary-scan cells with improved timing characteristics
|
US6397374B1
(en)
*
|
1998-09-30 |
2002-05-28 |
National Semiconductor Corporation |
Zero hold time circuit for high speed bus applications
|
KR100333640B1
(ko)
*
|
1998-12-30 |
2002-06-20 |
박종섭 |
메모리바운더리용의사스캔셀
|
US6175230B1
(en)
|
1999-01-14 |
2001-01-16 |
Genrad, Inc. |
Circuit-board tester with backdrive-based burst timing
|
FR2790832B1
(fr)
*
|
1999-03-08 |
2001-06-08 |
France Telecom |
Procede de test de circuits integres avec acces a des points de memorisation du circuit
|
JP3361472B2
(ja)
*
|
1999-04-02 |
2003-01-07 |
松下電器産業株式会社 |
アナログ・バウンダリ・スキャン対応集積回路装置
|
WO2000073809A1
(fr)
*
|
1999-05-26 |
2000-12-07 |
Hitachi, Ltd. |
Circuit integre a semi-conducteur
|
US6453448B1
(en)
*
|
1999-06-03 |
2002-09-17 |
Micron Technology, Inc. |
Functional level configuration of input-output test circuitry
|
US6311318B1
(en)
*
|
1999-07-13 |
2001-10-30 |
Vlsi Technology, Inc. |
Design for test area optimization algorithm
|
JP4428489B2
(ja)
*
|
1999-08-23 |
2010-03-10 |
パナソニック株式会社 |
集積回路装置及びそのテスト方法
|
US6430718B1
(en)
*
|
1999-08-30 |
2002-08-06 |
Cypress Semiconductor Corp. |
Architecture, circuitry and method for testing one or more integrated circuits and/or receiving test information therefrom
|
US6532557B1
(en)
*
|
1999-09-23 |
2003-03-11 |
Silicon Motion, Inc. |
Method and apparatus for improving fault test coverage for an integrated circuit
|
DE19948902C1
(de)
*
|
1999-10-11 |
2001-07-12 |
Infineon Technologies Ag |
Schaltungszelle zur Testmuster-Generierung und Testmuster-Kompression
|
JP3339479B2
(ja)
*
|
1999-10-13 |
2002-10-28 |
日本電気株式会社 |
クロック制御回路および方法
|
US6598191B1
(en)
*
|
1999-11-23 |
2003-07-22 |
Hewlett-Packard Development Companay, L.P. |
Verification of asynchronous boundary behavior
|
US6543018B1
(en)
*
|
1999-12-02 |
2003-04-01 |
Koninklijke Philips Electronics N.V. |
System and method to facilitate flexible control of bus drivers during scan test operations
|
JP4002378B2
(ja)
*
|
1999-12-27 |
2007-10-31 |
エルピーダメモリ株式会社 |
電子回路
|
US6662324B1
(en)
*
|
1999-12-28 |
2003-12-09 |
International Business Machines Corporation |
Global transition scan based AC method
|
US6453436B1
(en)
*
|
1999-12-28 |
2002-09-17 |
International Business Machines Corporation |
Method and apparatus for improving transition fault testability of semiconductor chips
|
US6625768B1
(en)
*
|
2000-03-29 |
2003-09-23 |
Intel Corporation |
Test bus architecture
|
US6567943B1
(en)
*
|
2000-04-07 |
2003-05-20 |
International Business Machines Corporation |
D flip-flop structure with flush path for high-speed boundary scan applications
|
US6567944B1
(en)
|
2000-04-25 |
2003-05-20 |
Sun Microsystems, Inc. |
Boundary scan cell design for high performance I/O cells
|
US6578168B1
(en)
|
2000-04-25 |
2003-06-10 |
Sun Microsystems, Inc. |
Method for operating a boundary scan cell design for high performance I/O cells
|
US6904553B1
(en)
*
|
2000-09-26 |
2005-06-07 |
Hewlett-Packard Development Company, L.P. |
Deterministic testing of edge-triggered logic
|
JP4748337B2
(ja)
*
|
2000-09-26 |
2011-08-17 |
大日本印刷株式会社 |
半導体回路のテスト用設計回路パタン
|
JP3727838B2
(ja)
*
|
2000-09-27 |
2005-12-21 |
株式会社東芝 |
半導体集積回路
|
US6650136B2
(en)
*
|
2001-02-16 |
2003-11-18 |
Intel Corporation |
Method and apparatus to enhance testability of logic coupled to IO buffers
|
JP2002351694A
(ja)
*
|
2001-05-23 |
2002-12-06 |
Nec Corp |
スキャンパステスト方法
|
US6594816B1
(en)
*
|
2001-06-05 |
2003-07-15 |
Cypress Semiconductor Corporation |
Method and an apparatus for synthesizing a programmable logic circuit
|
DE10132159B4
(de)
*
|
2001-07-03 |
2004-03-11 |
Infineon Technologies Ag |
Verfahren und Vorrichtung zum gleichzeitigen Testen einer Mehrzahl von integrierten Schaltungen
|
DE10136703C1
(de)
*
|
2001-07-27 |
2003-04-17 |
Infineon Technologies Ag |
Logikvorrichtung zum Testen einer integrierten Schaltung
|
EP1417502B1
(de)
|
2001-08-16 |
2007-10-17 |
Nxp B.V. |
Elektronischer schaltkreis und testverfahren
|
US7343535B2
(en)
*
|
2002-02-06 |
2008-03-11 |
Avago Technologies General Ip Dte Ltd |
Embedded testing capability for integrated serializer/deserializers
|
US6941498B2
(en)
*
|
2002-03-07 |
2005-09-06 |
Agilent Technologies, Inc. |
Technique for debugging an integrated circuit having a parallel scan-chain architecture
|
JP3484181B1
(ja)
*
|
2002-09-02 |
2004-01-06 |
沖電気工業株式会社 |
半導体テスト回路
|
US7149942B2
(en)
*
|
2002-12-16 |
2006-12-12 |
Renesas Technology Corp. |
Semiconductor integrated circuit with test circuit
|
US7145977B2
(en)
*
|
2003-07-30 |
2006-12-05 |
International Business Machines Corporation |
Diagnostic method and apparatus for non-destructively observing latch data
|
US6979996B2
(en)
*
|
2003-09-15 |
2005-12-27 |
International Business Machines Corporation |
Apparatus and method for automatic elimination of round-trip delay errors induced by automatic test equipment calibration
|
US6982437B2
(en)
*
|
2003-09-19 |
2006-01-03 |
Agilent Technologies, Inc. |
Surface emitting laser package having integrated optical element and alignment post
|
US7520679B2
(en)
*
|
2003-09-19 |
2009-04-21 |
Avago Technologies Fiber Ip (Singapore) Pte. Ltd. |
Optical device package with turning mirror and alignment post
|
US6953990B2
(en)
*
|
2003-09-19 |
2005-10-11 |
Agilent Technologies, Inc. |
Wafer-level packaging of optoelectronic devices
|
US20050063648A1
(en)
*
|
2003-09-19 |
2005-03-24 |
Wilson Robert Edward |
Alignment post for optical subassemblies made with cylindrical rods, tubes, spheres, or similar features
|
US20050063431A1
(en)
*
|
2003-09-19 |
2005-03-24 |
Gallup Kendra J. |
Integrated optics and electronics
|
US7162673B2
(en)
*
|
2003-11-14 |
2007-01-09 |
Integrated Device Technology, Inc. |
Scan chain registers that utilize feedback paths within latch units to support toggling of latch unit outputs during enhanced delay fault testing
|
US20050213995A1
(en)
*
|
2004-03-26 |
2005-09-29 |
Myunghee Lee |
Low power and low jitter optical receiver for fiber optic communication link
|
US7353470B2
(en)
*
|
2005-02-14 |
2008-04-01 |
On-Chip Technologies, Inc. |
Variable clocked scan test improvements
|
JP2007011957A
(ja)
*
|
2005-07-04 |
2007-01-18 |
Nec Electronics Corp |
回路設計装置およびプログラム
|
US20070051949A1
(en)
*
|
2005-09-06 |
2007-03-08 |
Peter Schneider |
Method and arrangment for testing a stacked die semiconductor device
|
JP2007218798A
(ja)
*
|
2006-02-17 |
2007-08-30 |
Nec Electronics Corp |
半導体集積回路装置
|
US7707467B2
(en)
*
|
2007-02-23 |
2010-04-27 |
Micron Technology, Inc. |
Input/output compression and pin reduction in an integrated circuit
|
US8135975B2
(en)
*
|
2007-03-09 |
2012-03-13 |
Analog Devices, Inc. |
Software programmable timing architecture
|
EP2331979B1
(de)
*
|
2008-09-26 |
2012-07-04 |
Nxp B.V. |
Verfahren zur prüfung einer teilweise zusammengebauten mehrchipanordnung, integrierter schaltungschip und mehrchipanordnung
|
US7908535B2
(en)
*
|
2009-06-30 |
2011-03-15 |
Texas Instruments Incorporated |
Scan testable register file
|
FR2972087B1
(fr)
*
|
2011-02-24 |
2014-05-30 |
Dolphin Integration Sa |
Circuit de bascule commandee par impulsions
|
US9086457B2
(en)
*
|
2013-03-26 |
2015-07-21 |
International Business Machines Corporation |
Scan chain latch design that improves testability of integrated circuits
|
US11073553B2
(en)
*
|
2017-12-29 |
2021-07-27 |
Texas Instruments Incorporated |
Dynamic generation of ATPG mode signals for testing multipath memory circuit
|
US11300614B1
(en)
*
|
2019-10-04 |
2022-04-12 |
Synopsys, Inc. |
Save and restore register
|
EP4180825A1
(de)
*
|
2021-11-12 |
2023-05-17 |
Samsung Electronics Co., Ltd. |
Testschaltung, die ein clock-gating-schema verwendet, um die capture-prozedur und den bypass-modus zu halten, und integrierte schaltung, die diese enthält
|
US11959965B2
(en)
|
2021-11-12 |
2024-04-16 |
Samsung Electronics Co., Ltd. |
Test circuit using clock gating scheme to hold capture procedure and bypass mode, and integrated circuit including the same
|