DE69002170D1 - Phasenregelschleife mit genauem frequenz- und phasenabgleich zweier signale. - Google Patents

Phasenregelschleife mit genauem frequenz- und phasenabgleich zweier signale.

Info

Publication number
DE69002170D1
DE69002170D1 DE9090101072T DE69002170T DE69002170D1 DE 69002170 D1 DE69002170 D1 DE 69002170D1 DE 9090101072 T DE9090101072 T DE 9090101072T DE 69002170 T DE69002170 T DE 69002170T DE 69002170 D1 DE69002170 D1 DE 69002170D1
Authority
DE
Germany
Prior art keywords
signals
phase
control loop
accurate frequency
phase control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE9090101072T
Other languages
English (en)
Other versions
DE69002170T2 (de
Inventor
Gary J Lesmeister
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Credence Systems Corp
Original Assignee
Asix Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asix Systems Corp filed Critical Asix Systems Corp
Publication of DE69002170D1 publication Critical patent/DE69002170D1/de
Application granted granted Critical
Publication of DE69002170T2 publication Critical patent/DE69002170T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B27/00—Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
DE90101072T 1989-01-30 1990-01-19 Phasenregelschleife mit genauem Frequenz- und Phasenabgleich zweier Signale. Expired - Fee Related DE69002170T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07303927 US4902986B1 (en) 1989-01-30 1989-01-30 Phased locked loop to provide precise frequency and phase tracking of two signals

Publications (2)

Publication Number Publication Date
DE69002170D1 true DE69002170D1 (de) 1993-08-19
DE69002170T2 DE69002170T2 (de) 1994-02-17

Family

ID=23174298

Family Applications (1)

Application Number Title Priority Date Filing Date
DE90101072T Expired - Fee Related DE69002170T2 (de) 1989-01-30 1990-01-19 Phasenregelschleife mit genauem Frequenz- und Phasenabgleich zweier Signale.

Country Status (4)

Country Link
US (1) US4902986B1 (de)
EP (1) EP0380979B1 (de)
JP (1) JP2976206B2 (de)
DE (1) DE69002170T2 (de)

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JPH04351008A (ja) * 1991-05-28 1992-12-04 Sony Corp ディジタルｖｃｏ
US6418424B1 (en) 1991-12-23 2002-07-09 Steven M. Hoffberg Ergonomic man-machine interface incorporating adaptive pattern recognition based control system
US8352400B2 (en) 1991-12-23 2013-01-08 Hoffberg Steven M Adaptive pattern recognition based controller apparatus and method and human-factored interface therefore
US6400996B1 (en) 1999-02-01 2002-06-04 Steven M. Hoffberg Adaptive pattern recognition based control system and method
US10361802B1 (en) 1999-02-01 2019-07-23 Blanding Hovenweep, Llc Adaptive pattern recognition based control system and method
US5903454A (en) 1991-12-23 1999-05-11 Hoffberg; Linda Irene Human-factored interface corporating adaptive pattern recognition based controller apparatus
US6850252B1 (en) * 1999-10-05 2005-02-01 Steven M. Hoffberg Intelligent electronic appliance system and method
US5278522A (en) * 1992-11-19 1994-01-11 Codex, Corp. High frequency voltage controlled oscillator
JP2996328B2 (ja) * 1992-12-17 1999-12-27 三菱電機株式会社 半導体集積回路、およびそれを用いた半導体集積回路組合回路
US5345186A (en) * 1993-01-19 1994-09-06 Credence Systems Corporation Retriggered oscillator for jitter-free phase locked loop frequency synthesis
US5552733A (en) * 1993-01-19 1996-09-03 Credence Systems Corporation Precise and agile timing signal generator based on a retriggered oscillator
US5611053A (en) * 1994-01-21 1997-03-11 Advanced Micro Devices, Inc. Apparatus and method for integrating bus master ownership of local bus load by plural data transceivers
US6295572B1 (en) * 1994-01-24 2001-09-25 Advanced Micro Devices, Inc. Integrated SCSI and ethernet controller on a PCI local bus
US6469493B1 (en) 1995-08-01 2002-10-22 Teradyne, Inc. Low cost CMOS tester with edge rate compensation
US5684421A (en) * 1995-10-13 1997-11-04 Credence Systems Corporation Compensated delay locked loop timing vernier
US6115769A (en) * 1996-06-28 2000-09-05 Lsi Logic Corporation Method and apparatus for providing precise circuit delays
US6115318A (en) * 1996-12-03 2000-09-05 Micron Technology, Inc. Clock vernier adjustment
US5940608A (en) * 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
US6912680B1 (en) 1997-02-11 2005-06-28 Micron Technology, Inc. Memory system with dynamic timing correction
US5920518A (en) * 1997-02-11 1999-07-06 Micron Technology, Inc. Synchronous clock generator including delay-locked loop
US5946244A (en) 1997-03-05 1999-08-31 Micron Technology, Inc. Delay-locked loop with binary-coupled capacitor
US6173432B1 (en) * 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US5953284A (en) * 1997-07-09 1999-09-14 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
US6073259A (en) * 1997-08-05 2000-06-06 Teradyne, Inc. Low cost CMOS tester with high channel density
US6011732A (en) * 1997-08-20 2000-01-04 Micron Technology, Inc. Synchronous clock generator including a compound delay-locked loop
US5940609A (en) * 1997-08-29 1999-08-17 Micorn Technology, Inc. Synchronous clock generator including a false lock detector
US5926047A (en) 1997-08-29 1999-07-20 Micron Technology, Inc. Synchronous clock generator including a delay-locked loop signal loss detector
US6101197A (en) * 1997-09-18 2000-08-08 Micron Technology, Inc. Method and apparatus for adjusting the timing of signals over fine and coarse ranges
US6487647B1 (en) * 1997-12-29 2002-11-26 Intel Corporation Adaptive memory interface timing generation
US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
US6016282A (en) * 1998-05-28 2000-01-18 Micron Technology, Inc. Clock vernier adjustment
US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6349399B1 (en) 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
US6029250A (en) * 1998-09-09 2000-02-22 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US7966078B2 (en) 1999-02-01 2011-06-21 Steven Hoffberg Network media appliance system and method
US6470060B1 (en) 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
US6294937B1 (en) 1999-05-25 2001-09-25 Lsi Logic Corporation Method and apparatus for self correcting parallel I/O circuitry
US6557066B1 (en) 1999-05-25 2003-04-29 Lsi Logic Corporation Method and apparatus for data dependent, dual level output driver
US6307496B1 (en) * 1999-10-04 2001-10-23 Denso Corporation Sensing apparatus including an A/D conversion circuit for detecting a physical quantity
US6801989B2 (en) * 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US6680874B1 (en) 2002-08-29 2004-01-20 Micron Technology, Inc. Delay lock loop circuit useful in a synchronous system and associated methods
US7256628B2 (en) * 2003-01-29 2007-08-14 Sun Microsystems, Inc. Speed-matching control method and circuit
US7168027B2 (en) 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
US7234070B2 (en) * 2003-10-27 2007-06-19 Micron Technology, Inc. System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
US20060095221A1 (en) * 2004-11-03 2006-05-04 Teradyne, Inc. Method and apparatus for controlling variable delays in electronic circuitry
US20080046789A1 (en) * 2006-08-21 2008-02-21 Igor Arsovski Apparatus and method for testing memory devices and circuits in integrated circuits
US7804371B2 (en) * 2006-12-31 2010-09-28 Sandisk Corporation Systems, modules, chips, circuits and methods with delay trim value updates on power-up
US7765445B2 (en) 2008-02-16 2010-07-27 International Business Machines Corporation Analog testing of ring oscillators using built-in self test apparatus
US20130226496A1 (en) * 2012-02-29 2013-08-29 Qualcomm Incorporated Precise calibration of electronic components
CN104764914A (zh) * 2014-01-03 2015-07-08 致茂电子股份有限公司 误差补偿方法与应用此方法的自动测试设备

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US4346343A (en) * 1980-05-16 1982-08-24 International Business Machines Corporation Power control means for eliminating circuit to circuit delay differences and providing a desired circuit delay
US4584695A (en) * 1983-11-09 1986-04-22 National Semiconductor Corporation Digital PLL decoder
US4641048A (en) * 1984-08-24 1987-02-03 Tektronix, Inc. Digital integrated circuit propagation delay time controller
US4813005A (en) * 1987-06-24 1989-03-14 Hewlett-Packard Company Device for synchronizing the output pulses of a circuit with an input clock

Also Published As

Publication number Publication date
US4902986A (en) 1990-02-20
JPH02251779A (ja) 1990-10-09
EP0380979B1 (de) 1993-07-14
US4902986B1 (en) 1998-09-01
JP2976206B2 (ja) 1999-11-10
EP0380979A2 (de) 1990-08-08
DE69002170T2 (de) 1994-02-17
EP0380979A3 (de) 1991-10-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN

8327 Change in the person/name/address of the patent owner

Owner name: CREDENCE SYSTEMS CORP. (N.D.GESETZEN D.STAATES DEL

8328 Change in the person/name/address of the agent

Free format text: ZIPSE & HABERSACK, 80639 MUENCHEN

8339 Ceased/non-payment of the annual fee