DE69008693T2 - Methode zur Herstellung eines Halbleiterbauelementes mit angeschrägten Öffnungen. - Google Patents

Methode zur Herstellung eines Halbleiterbauelementes mit angeschrägten Öffnungen.

Info

Publication number
DE69008693T2
DE69008693T2 DE69008693T DE69008693T DE69008693T2 DE 69008693 T2 DE69008693 T2 DE 69008693T2 DE 69008693 T DE69008693 T DE 69008693T DE 69008693 T DE69008693 T DE 69008693T DE 69008693 T2 DE69008693 T2 DE 69008693T2
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
tapered openings
tapered
openings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69008693T
Other languages
English (en)
Other versions
DE69008693D1 (de
Inventor
Tatsuro Mitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69008693D1 publication Critical patent/DE69008693D1/de
Publication of DE69008693T2 publication Critical patent/DE69008693T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/7605Making of isolation regions between components between components manufactured in an active substrate comprising AIII BV compounds
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/131Reactive ion etching rie
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/978Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
DE69008693T 1989-12-22 1990-12-20 Methode zur Herstellung eines Halbleiterbauelementes mit angeschrägten Öffnungen. Expired - Fee Related DE69008693T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1334548A JPH07111966B2 (ja) 1989-12-22 1989-12-22 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69008693D1 DE69008693D1 (de) 1994-06-09
DE69008693T2 true DE69008693T2 (de) 1994-09-15

Family

ID=18278648

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69008693T Expired - Fee Related DE69008693T2 (de) 1989-12-22 1990-12-20 Methode zur Herstellung eines Halbleiterbauelementes mit angeschrägten Öffnungen.

Country Status (4)

Country Link
US (1) US5356823A (de)
EP (1) EP0436192B1 (de)
JP (1) JPH07111966B2 (de)
DE (1) DE69008693T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5663075A (en) * 1994-07-14 1997-09-02 The United States Of America As Represented By The Secretary Of The Air Force Method of fabricating backside illuminated FET optical receiver with gallium arsenide species
US5514605A (en) * 1994-08-24 1996-05-07 Nec Corporation Fabrication process for compound semiconductor device
JPH09283621A (ja) * 1996-04-10 1997-10-31 Murata Mfg Co Ltd 半導体装置のt型ゲート電極形成方法およびその構造
TW407309B (en) * 1999-01-29 2000-10-01 Nat Science Council MOSFET manufacturing process
FR2827041B1 (fr) * 2001-07-03 2003-12-12 Commissariat Energie Atomique Dispositif piezoresistif et procedes de fabrication de ce dispositif
US6455383B1 (en) * 2001-10-25 2002-09-24 Silicon-Based Technology Corp. Methods of fabricating scaled MOSFETs
JP4046586B2 (ja) * 2002-01-16 2008-02-13 シャープ株式会社 化合物半導体素子及びその製造方法
CN1267780C (zh) * 2002-11-11 2006-08-02 Lg.飞利浦Lcd有限公司 用于液晶显示器的阵列基板及其制造方法
US8193591B2 (en) * 2006-04-13 2012-06-05 Freescale Semiconductor, Inc. Transistor and method with dual layer passivation
US9601638B2 (en) * 2011-10-19 2017-03-21 Nxp Usa, Inc. GaN-on-Si switch devices

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Publication number Priority date Publication date Assignee Title
US4040168A (en) * 1975-11-24 1977-08-09 Rca Corporation Fabrication method for a dual gate field-effect transistor
US4029531A (en) * 1976-03-29 1977-06-14 Rca Corporation Method of forming grooves in the [011] crystalline direction
US4448797A (en) * 1981-02-04 1984-05-15 Xerox Corporation Masking techniques in chemical vapor deposition
JPS582030A (ja) * 1981-06-29 1983-01-07 Nec Corp 半導体結晶の加工方法
JPH0665225B2 (ja) * 1984-01-13 1994-08-22 株式会社東芝 半導体記憶装置の製造方法
US4484979A (en) * 1984-04-16 1984-11-27 At&T Bell Laboratories Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer
JPS61124137A (ja) * 1984-11-20 1986-06-11 Fujitsu Ltd 微細開孔パタ−ンの形成方法
JPS61161715A (ja) * 1985-01-10 1986-07-22 Matsushita Electronics Corp 半導体装置の製造方法
JPS6230323A (ja) * 1985-07-31 1987-02-09 Toshiba Corp 微細加工方法
JPS6281769A (ja) * 1985-10-07 1987-04-15 Nippon Telegr & Teleph Corp <Ntt> 電界効果トランジスタの製造方法
JPS62130541A (ja) * 1985-12-03 1987-06-12 Toshiba Corp 半導体装置の製造方法
JPS62158363A (ja) * 1985-12-28 1987-07-14 Matsushita Electronics Corp 半導体装置の製造方法
DE3609274A1 (de) * 1986-03-19 1987-09-24 Siemens Ag Verfahren zur herstellung eines selbstjustiert positionierten metallkontaktes
US4702000A (en) * 1986-03-19 1987-10-27 Harris Corporation Technique for elimination of polysilicon stringers in direct moat field oxide structure
JPS63137428A (ja) * 1986-11-29 1988-06-09 Sony Corp ドライエツチング方法
JPS63278337A (ja) * 1987-05-11 1988-11-16 Fujitsu Ltd 半導体装置の製造方法
JPS63287068A (ja) * 1987-05-19 1988-11-24 Sanyo Electric Co Ltd 半導体装置の製造方法
JPS63296352A (ja) * 1987-05-28 1988-12-02 Matsushita Electric Ind Co Ltd 電極配線形成方法
JPH0834311B2 (ja) * 1987-06-10 1996-03-29 日本電装株式会社 半導体装置の製造方法
JPS6428923A (en) * 1987-07-24 1989-01-31 Fujitsu Ltd Formation of taper-shaped trench
JP2612836B2 (ja) * 1987-09-23 1997-05-21 シーメンス、アクチエンゲゼルシヤフト 自己整合ゲートを備えるmesfetの製造方法
JPH0220021A (ja) * 1988-07-07 1990-01-23 Nec Corp 半導体装置の制造方法
JPH0258222A (ja) * 1988-08-23 1990-02-27 Oki Electric Ind Co Ltd パターン形成方法
US4960723A (en) * 1989-03-30 1990-10-02 Motorola, Inc. Process for making a self aligned vertical field effect transistor having an improved source contact
EP0414372A3 (en) * 1989-07-21 1991-04-24 Sony Corporation Dry etching methods

Also Published As

Publication number Publication date
JPH07111966B2 (ja) 1995-11-29
US5356823A (en) 1994-10-18
DE69008693D1 (de) 1994-06-09
JPH03194931A (ja) 1991-08-26
EP0436192B1 (de) 1994-05-04
EP0436192A1 (de) 1991-07-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee