DE69012355D1 - Architektur einer programmierten Logik mit mehreren Seiten. - Google Patents

Architektur einer programmierten Logik mit mehreren Seiten.

Info

Publication number
DE69012355D1
DE69012355D1 DE69012355T DE69012355T DE69012355D1 DE 69012355 D1 DE69012355 D1 DE 69012355D1 DE 69012355 T DE69012355 T DE 69012355T DE 69012355 T DE69012355 T DE 69012355T DE 69012355 D1 DE69012355 D1 DE 69012355D1
Authority
DE
Germany
Prior art keywords
multiple pages
programmed logic
logic architecture
architecture
programmed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69012355T
Other languages
English (en)
Other versions
DE69012355T2 (de
Inventor
Scott K Pickett
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Application granted granted Critical
Publication of DE69012355D1 publication Critical patent/DE69012355D1/de
Publication of DE69012355T2 publication Critical patent/DE69012355T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable
DE69012355T 1989-01-19 1990-01-12 Architektur einer programmierten Logik mit mehreren Seiten. Expired - Lifetime DE69012355T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/299,047 US4942319A (en) 1989-01-19 1989-01-19 Multiple page programmable logic architecture

Publications (2)

Publication Number Publication Date
DE69012355D1 true DE69012355D1 (de) 1994-10-20
DE69012355T2 DE69012355T2 (de) 1995-05-04

Family

ID=23153084

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69012355T Expired - Lifetime DE69012355T2 (de) 1989-01-19 1990-01-12 Architektur einer programmierten Logik mit mehreren Seiten.

Country Status (6)

Country Link
US (1) US4942319A (de)
EP (1) EP0379071B1 (de)
JP (1) JP3212303B2 (de)
KR (1) KR900012145A (de)
CA (1) CA1331638C (de)
DE (1) DE69012355T2 (de)

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US5343406A (en) * 1989-07-28 1994-08-30 Xilinx, Inc. Distributed memory architecture for a configurable logic array and method for using distributed memory
JPH0756749B2 (ja) * 1989-09-29 1995-06-14 株式会社東芝 機能選択回路
US5247213A (en) * 1990-05-08 1993-09-21 Advanced Micro Devices, Inc. Programmable sense amplifier power reduction
US5072138A (en) * 1990-08-17 1991-12-10 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with sequential clocked access codes for test mode entry
DE69120483T2 (de) * 1990-08-17 1996-11-14 Sgs Thomson Microelectronics Halbleiter-Speicher mit unterdrücktem Testmodus-Eingang während des Strom-Einschaltens
US5072137A (en) * 1990-08-17 1991-12-10 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with a clocked access code for test mode entry
US5189628A (en) * 1991-03-11 1993-02-23 National Semiconductor Corporation System and method for partitioning PLA product terms into distinct logical groups
US5384499A (en) * 1991-04-25 1995-01-24 Altera Corporation High-density erasable programmable logic device architecture using multiplexer interconnections
US5861760A (en) 1991-04-25 1999-01-19 Altera Corporation Programmable logic device macrocell with improved capability
US5130574A (en) * 1991-05-06 1992-07-14 Lattice Semiconductor Corporation Programmable logic device providing product term sharing and steering to the outputs of the programmable logic device
US5189320A (en) * 1991-09-23 1993-02-23 Atmel Corporation Programmable logic device with multiple shared logic arrays
US5250859A (en) * 1991-09-27 1993-10-05 Kaplinsky Cecil H Low power multifunction logic array
GB9223226D0 (en) 1992-11-05 1992-12-16 Algotronix Ltd Improved configurable cellular array (cal ii)
US5357152A (en) * 1992-11-10 1994-10-18 Infinite Technology Corporation Logic system of logic networks with programmable selected functions and programmable operational controls
US5455525A (en) * 1993-12-06 1995-10-03 Intelligent Logic Systems, Inc. Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array
JP2001520812A (ja) * 1994-09-26 2001-10-30 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ 組合されたプログラム可能論理アレーとアレー論理
US5696692A (en) * 1995-04-24 1997-12-09 Cadence Design Systems, Inc. Conditional selection method for reducing power consumption in a circuit
US5640106A (en) * 1995-05-26 1997-06-17 Xilinx, Inc. Method and structure for loading data into several IC devices
US5944803A (en) * 1997-03-25 1999-08-31 Sony Corporation Isolatable multi-point serial communication utilizing a single universal asynchronous receiver and transmitter (UART)
US6314549B1 (en) * 1998-01-09 2001-11-06 Jeng-Jye Shau Power saving methods for programmable logic arrays
US6034538A (en) * 1998-01-21 2000-03-07 Lucent Technologies Inc. Virtual logic system for reconfigurable hardware
JP3540796B2 (ja) * 2001-12-28 2004-07-07 東京エレクトロンデバイス株式会社 演算システム
US20070038971A1 (en) * 2003-09-30 2007-02-15 Tatsuo Hiramatsu Processing device with reconfigurable circuit, integrated circuit device and processing method using these devices
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics

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US3593317A (en) * 1969-12-30 1971-07-13 Ibm Partitioning logic operations in a generalized matrix system
US3849638A (en) * 1973-07-18 1974-11-19 Gen Electric Segmented associative logic circuits
US4034356A (en) * 1975-12-03 1977-07-05 Ibm Corporation Reconfigurable logic array
US4124899A (en) * 1977-05-23 1978-11-07 Monolithic Memories, Inc. Programmable array logic circuit
JPS5483340A (en) * 1977-12-15 1979-07-03 Nec Corp Logic array
US4233667A (en) * 1978-10-23 1980-11-11 International Business Machines Corporation Demand powered programmable logic array
US4293783A (en) * 1978-11-01 1981-10-06 Massachusetts Institute Of Technology Storage/logic array
US4415818A (en) * 1979-01-16 1983-11-15 Nippon Telegraph & Telephone Corp. Programmable sequential logic circuit devices
US4495590A (en) * 1980-12-31 1985-01-22 International Business Machines Corporation PLA With time division multiplex feature for improved density
US4422072A (en) * 1981-07-30 1983-12-20 Signetics Corporation Field programmable logic array circuit
JPS5885638A (ja) * 1981-11-17 1983-05-23 Ricoh Co Ltd プログラマブルロジツクアレイ
US4660171A (en) * 1981-12-21 1987-04-21 International Business Machines Corp. Apparatus and method using a programmable logic array for decoding an operation code and providing a plurality of sequential output states
US4583193A (en) * 1982-02-22 1986-04-15 International Business Machines Corp. Integrated circuit mechanism for coupling multiple programmable logic arrays to a common bus
US4506341A (en) * 1982-06-10 1985-03-19 International Business Machines Corporation Interlaced programmable logic array having shared elements
US4506173A (en) * 1982-10-25 1985-03-19 Burroughs Corporation Low power partitioned PLA
US4758993A (en) * 1984-11-19 1988-07-19 Fujitsu Limited Random access memory device formed on a semiconductor substrate having an array of memory cells divided into sub-arrays
US4742252A (en) * 1985-03-29 1988-05-03 Advanced Micro Devices, Inc. Multiple array customizable logic device
US4677318A (en) * 1985-04-12 1987-06-30 Altera Corporation Programmable logic storage element for programmable logic devices
JPS61294562A (ja) * 1985-06-21 1986-12-25 Mitsubishi Electric Corp 半導体記憶装置
US4758746A (en) * 1985-08-12 1988-07-19 Monolithic Memories, Inc. Programmable logic array with added array of gates and added output routing flexibility
JPH0736269B2 (ja) * 1985-08-30 1995-04-19 株式会社日立製作所 半導体記憶装置
US4763020B1 (en) * 1985-09-06 1997-07-08 Ricoh Kk Programmable logic device having plural programmable function cells
US4703206A (en) * 1985-11-19 1987-10-27 Signetics Corporation Field-programmable logic device with programmable foldback to control number of logic levels
DE3543471C1 (de) * 1985-12-09 1992-01-09 Nixdorf Computer Ag In integrierter Technik hergestellter Baustein zur Erstellung integrierter Schaltungen
JPS62220879A (ja) * 1986-03-22 1987-09-29 Hitachi Ltd 半導体装置
US4675556A (en) * 1986-06-09 1987-06-23 Intel Corporation Binomially-encoded finite state machine
JPS648723A (en) * 1987-06-30 1989-01-12 Mitsubishi Electric Corp Logic device

Also Published As

Publication number Publication date
KR900012145A (ko) 1990-08-03
EP0379071A3 (en) 1990-10-31
EP0379071B1 (de) 1994-09-14
US4942319A (en) 1990-07-17
DE69012355T2 (de) 1995-05-04
JP3212303B2 (ja) 2001-09-25
CA1331638C (en) 1994-08-23
EP0379071A2 (de) 1990-07-25
JPH0340520A (ja) 1991-02-21

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