DE69017303T2 - Testverfahren für eine integrierte Schaltung mit nichtflüchtiger Speicherzelle fähig zum zeitweiligen Halten von Information. - Google Patents
Testverfahren für eine integrierte Schaltung mit nichtflüchtiger Speicherzelle fähig zum zeitweiligen Halten von Information.Info
- Publication number
- DE69017303T2 DE69017303T2 DE69017303T DE69017303T DE69017303T2 DE 69017303 T2 DE69017303 T2 DE 69017303T2 DE 69017303 T DE69017303 T DE 69017303T DE 69017303 T DE69017303 T DE 69017303T DE 69017303 T2 DE69017303 T2 DE 69017303T2
- Authority
- DE
- Germany
- Prior art keywords
- integrated circuit
- memory cell
- volatile memory
- test method
- holding information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1202—Word line control
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5002—Characteristic
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Logic Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1206396A JP2726503B2 (ja) | 1989-08-09 | 1989-08-09 | 集積回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69017303D1 DE69017303D1 (de) | 1995-04-06 |
DE69017303T2 true DE69017303T2 (de) | 1995-06-29 |
Family
ID=16522663
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69017303T Expired - Fee Related DE69017303T2 (de) | 1989-08-09 | 1990-08-07 | Testverfahren für eine integrierte Schaltung mit nichtflüchtiger Speicherzelle fähig zum zeitweiligen Halten von Information. |
Country Status (6)
Country | Link |
---|---|
US (1) | US5126969A (de) |
EP (1) | EP0412781B1 (de) |
JP (1) | JP2726503B2 (de) |
KR (1) | KR910005463A (de) |
CA (1) | CA2022864A1 (de) |
DE (1) | DE69017303T2 (de) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04289593A (ja) * | 1991-03-19 | 1992-10-14 | Fujitsu Ltd | 不揮発性半導体記憶装置 |
KR0156590B1 (ko) * | 1993-05-11 | 1998-12-01 | 미요시 순키치 | 비소멸성 메모리장치, 비소멸성 메모리셀 및 다수의 트랜지스터의 각각과 비소멸성 메모리셀의 스레솔드값의 조절방법 |
JPH0778484A (ja) * | 1993-07-13 | 1995-03-20 | Nkk Corp | 記憶素子、不揮発性メモリ、不揮発性記憶装置及びそれを用いた情報記憶方法 |
US5623444A (en) * | 1994-08-25 | 1997-04-22 | Nippon Kokan Kk | Electrically-erasable ROM with pulse-driven memory cell transistors |
US5808338A (en) * | 1994-11-11 | 1998-09-15 | Nkk Corporation | Nonvolatile semiconductor memory |
US5661686A (en) * | 1994-11-11 | 1997-08-26 | Nkk Corporation | Nonvolatile semiconductor memory |
US5602779A (en) * | 1994-11-11 | 1997-02-11 | Nkk Corporation | Nonvolatile multivalue memory |
JPH08329691A (ja) * | 1995-05-30 | 1996-12-13 | Nkk Corp | 不揮発性半導体記憶装置 |
JPH0945090A (ja) * | 1995-07-31 | 1997-02-14 | Nkk Corp | 不揮発性半導体記憶装置 |
JPH0945094A (ja) * | 1995-07-31 | 1997-02-14 | Nkk Corp | 不揮発性半導体記憶装置 |
US6266272B1 (en) * | 1999-07-30 | 2001-07-24 | International Business Machines Corporation | Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cells |
US7016219B1 (en) * | 2003-12-16 | 2006-03-21 | Xilinx, Inc. | Single transistor non-volatile memory system, design, and operation |
TWI652683B (zh) * | 2017-10-13 | 2019-03-01 | 力旺電子股份有限公司 | 用於記憶體的電壓驅動器 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2442132C3 (de) * | 1974-09-03 | 1981-11-05 | Siemens AG, 1000 Berlin und 8000 München | Dynamisches Schieberegister und Verfahren zu seinem Betrieb |
FR2300391A1 (fr) * | 1976-02-06 | 1976-09-03 | Honeywell Inc | Memoire remanente a acces selectif |
US4112510A (en) * | 1977-05-25 | 1978-09-05 | Roger Thomas Baker | Dynamic memory cell with automatic refreshing |
US4715014A (en) * | 1985-10-29 | 1987-12-22 | Texas Instruments Incorporated | Modified three transistor EEPROM cell |
JPS62154786A (ja) * | 1985-12-27 | 1987-07-09 | Toshiba Corp | 不揮発性半導体メモリ |
JPS62229870A (ja) * | 1986-01-22 | 1987-10-08 | Mitsubishi Electric Corp | 半導体集積回路 |
US4788663A (en) * | 1987-04-24 | 1988-11-29 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device with a lightly-doped drain structure |
US4809225A (en) * | 1987-07-02 | 1989-02-28 | Ramtron Corporation | Memory cell with volatile and non-volatile portions having ferroelectric capacitors |
US4885719A (en) * | 1987-08-19 | 1989-12-05 | Ict International Cmos Technology, Inc. | Improved logic cell array using CMOS E2 PROM cells |
US4829203A (en) * | 1988-04-20 | 1989-05-09 | Texas Instruments Incorporated | Integrated programmable bit circuit with minimal power requirement |
-
1989
- 1989-08-09 JP JP1206396A patent/JP2726503B2/ja not_active Expired - Fee Related
-
1990
- 1990-08-06 US US07/563,193 patent/US5126969A/en not_active Expired - Fee Related
- 1990-08-07 DE DE69017303T patent/DE69017303T2/de not_active Expired - Fee Related
- 1990-08-07 EP EP90308688A patent/EP0412781B1/de not_active Expired - Lifetime
- 1990-08-08 CA CA002022864A patent/CA2022864A1/en not_active Abandoned
- 1990-08-09 KR KR1019900012240A patent/KR910005463A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
US5126969A (en) | 1992-06-30 |
JPH0370211A (ja) | 1991-03-26 |
JP2726503B2 (ja) | 1998-03-11 |
EP0412781A1 (de) | 1991-02-13 |
EP0412781B1 (de) | 1995-03-01 |
DE69017303D1 (de) | 1995-04-06 |
KR910005463A (ko) | 1991-03-30 |
CA2022864A1 (en) | 1991-02-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE68919393D1 (de) | Nichtflüchtige Speicherzelle und Verfahren zum Lesen. | |
DE3872673D1 (de) | Verfahren zum testen von zellen von elektrisch programmierbaren speichern und entsprechende integrierte schaltung. | |
DE68923828T2 (de) | Architektur und Schnittstelle für Speicherkarten. | |
DE226494T1 (de) | System mit elektronenstrahlpruefsonde zum analysieren integrierter schaltungen. | |
DE59007516D1 (de) | Prüfvorrichtung zum prüfen von elektrischen oder elektronischen prüflingen. | |
DE69125225T2 (de) | Halbleiterspeicher mit Mehrfachtakt zum Eintritt im Prüfmodus | |
DE69013250D1 (de) | Leseanordnung für eine Halbleiterspeicheranordnung. | |
DE3685078D1 (de) | Speicherpruefgeraet. | |
DE3587858D1 (de) | IC-Testvorrichtung. | |
DE69019402T2 (de) | Prüfverfahren und -gerät für integrierte Schaltungen. | |
DE69030894D1 (de) | Speichermedium, Speicherungsverfahren und Verfahren zum Auslesen der gespeicherten Informationen | |
DE69419951T2 (de) | Halbleiterspeicher mit eingebauter Einbrennprüfung | |
DE68912458D1 (de) | Speicherprüfgerät. | |
DE69017303D1 (de) | Testverfahren für eine integrierte Schaltung mit nichtflüchtiger Speicherzelle fähig zum zeitweiligen Halten von Information. | |
DE3885594T2 (de) | Speicherprüfgerät. | |
DE3687859T2 (de) | Verfahren und geraet zum lesen von strichcode. | |
DE3789726T2 (de) | Register mit Einrichtungen zum gleichzeitigen Auslesen und Einschreiben über vielfache Anschlüsse. | |
DE3850547T2 (de) | Speicher mit eingebautem Logik-LSI und Verfahren zum LSI-Prüfen. | |
DE69431794T2 (de) | LESE-/SCHREIBVORRICHTUNG FüR EINE IC-KARTE UND STEUERVERFAHREN DAFüR | |
DE68912557D1 (de) | Verfahren und gerät zum lesen von zeichen. | |
DE3862168D1 (de) | Elektronischer pruefstand zum schnellen eichen von wasserzaehlern. | |
AT382487B (de) | Vorrichtung zum auslesen von information | |
KR870003509A (ko) | 프로그램 가능한 장치의 불량 메모리 셀을 검출하는 시험방법 | |
DE69022975D1 (de) | Mehrfache Speichermodusauswahl für IC-Speicherchip. | |
DE3766393D1 (de) | Datenleseschaltung zum gebrauch in halbleiterspeichereinrichtungen. |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: KAWASAKI STEEL MICROELECTRONICS, INC., CHIBA, JP |
|
8339 | Ceased/non-payment of the annual fee |