Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
  • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
  • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
  • G11C11/419—Read-write [R-W] circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
  • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters

Applications Claiming Priority (1)

Publications (2)

Family

ID=10653665

Family Applications (2)

Family Applications Before (1)

Country Status (5)

Families Citing this family (18)

Family Cites Families (5)

• 1989
  • 1989-03-20 GB GB898906354A patent/GB8906354D0/en active Pending
• 1990
  • 1990-03-06 DE DE69020764A patent/DE69020764D1/de not_active Expired - Fee Related
  • 1990-03-06 EP EP90302343A patent/EP0389142B1/de not_active Expired - Lifetime
  • 1990-03-06 DE DE69020764T patent/DE69020764T4/de not_active Expired - Lifetime
  • 1990-03-15 JP JP2065505A patent/JP2763372B2/ja not_active Expired - Lifetime
  • 1990-03-16 US US07/494,681 patent/US5036494A/en not_active Expired - Lifetime

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