DE69022874T2 - Mehrlagen-Metallverbindungen für VLSI und Verfahren zum Herstellen derselben. - Google Patents

Mehrlagen-Metallverbindungen für VLSI und Verfahren zum Herstellen derselben.

Info

Publication number
DE69022874T2
DE69022874T2 DE69022874T DE69022874T DE69022874T2 DE 69022874 T2 DE69022874 T2 DE 69022874T2 DE 69022874 T DE69022874 T DE 69022874T DE 69022874 T DE69022874 T DE 69022874T DE 69022874 T2 DE69022874 T2 DE 69022874T2
Authority
DE
Germany
Prior art keywords
vlsi
making
methods
same
metal interconnects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69022874T
Other languages
English (en)
Other versions
DE69022874D1 (de
Inventor
Osamu Kudoh
Kenji Okada
Hiroshi Shiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69022874D1 publication Critical patent/DE69022874D1/de
Publication of DE69022874T2 publication Critical patent/DE69022874T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
DE69022874T 1989-04-05 1990-04-05 Mehrlagen-Metallverbindungen für VLSI und Verfahren zum Herstellen derselben. Expired - Fee Related DE69022874T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1087513A JPH02265243A (ja) 1989-04-05 1989-04-05 多層配線およびその形成方法

Publications (2)

Publication Number Publication Date
DE69022874D1 DE69022874D1 (de) 1995-11-16
DE69022874T2 true DE69022874T2 (de) 1996-04-18

Family

ID=13917069

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69022874T Expired - Fee Related DE69022874T2 (de) 1989-04-05 1990-04-05 Mehrlagen-Metallverbindungen für VLSI und Verfahren zum Herstellen derselben.

Country Status (4)

Country Link
US (1) US5248854A (de)
EP (1) EP0394722B1 (de)
JP (1) JPH02265243A (de)
DE (1) DE69022874T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5436411A (en) * 1993-12-20 1995-07-25 Lsi Logic Corporation Fabrication of substrates for multi-chip modules
JPH08111460A (ja) * 1994-08-16 1996-04-30 Nec Corp 多層配線の構造および製造方法
JPH098133A (ja) * 1995-06-22 1997-01-10 Nec Corp 半導体集積回路装置
US5699047A (en) * 1996-01-19 1997-12-16 Minnesota Mining And Manufacturing Co. Electronic article surveillance markers for direct application to optically recorded media
US6054389A (en) * 1997-12-29 2000-04-25 Vanguard International Semiconductor Corporation Method of forming metal conducting pillars
GB2346009B (en) 1999-01-13 2002-03-20 Lucent Technologies Inc Define via in dual damascene process
JP3418615B2 (ja) * 2001-06-12 2003-06-23 沖電気工業株式会社 半導体素子およびその製造方法
JP2003188252A (ja) * 2001-12-13 2003-07-04 Toshiba Corp 半導体装置及びその製造方法
JP2005328025A (ja) * 2004-04-13 2005-11-24 Matsushita Electric Ind Co Ltd 面実装電子部品の製造方法とこの製造方法で製造した面実装電子部品とこれを用いた電子機器
JP2006108211A (ja) 2004-10-01 2006-04-20 North:Kk 配線板と、その配線板を用いた多層配線基板と、その多層配線基板の製造方法
DE102007034402B4 (de) * 2006-12-14 2014-06-18 Advanpack Solutions Pte. Ltd. Halbleiterpackung und Herstellungsverfahren dafür
CN103137570B (zh) 2011-11-29 2016-02-10 先进封装技术私人有限公司 基板结构、半导体封装元件及基板结构的制造方法
JP2018100249A (ja) * 2016-12-21 2018-06-28 メルク パテント ゲゼルシャフト ミット ベシュレンクテル ハフツングＭｅｒｃｋ Ｐａｔｅｎｔ Ｇｅｓｅｌｌｓｃｈａｆｔ ｍｉｔ ｂｅｓｃｈｒａｅｎｋｔｅｒ Ｈａｆｔｕｎｇ 新規化合物、半導体材料、およびこれを用いた膜および半導体の製造方法
EP3671821A1 (de) * 2018-12-19 2020-06-24 IMEC vzw Verbindungssystem eines integrierten schaltkreises

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3718936A (en) * 1971-06-16 1973-02-27 American Express Invest Electrostatic matrix head construction
US3757028A (en) * 1972-09-18 1973-09-04 J Schlessel Terference printed board and similar transmission line structure for reducing in
FR2204940B1 (de) * 1972-10-27 1976-01-30 Thomson Csf Fr
FR2404990A1 (fr) * 1977-10-03 1979-04-27 Cii Honeywell Bull Substrat d'interconnexion de composants electroniques a circuits integres, muni d'un dispositif de reparation
JPS5729185U (de) * 1980-07-28 1982-02-16
US4487993A (en) * 1981-04-01 1984-12-11 General Electric Company High density electronic circuits having very narrow conductors
US4543715A (en) * 1983-02-28 1985-10-01 Allied Corporation Method of forming vertical traces on printed circuit board
GB8316476D0 (en) * 1983-06-16 1983-07-20 Plessey Co Plc Producing layered structure
US4601915A (en) * 1984-09-24 1986-07-22 Motorola, Inc. Method of fabricating air supported crossovers
JPS61219158A (ja) * 1985-03-25 1986-09-29 Mitsubishi Electric Corp 半導体装置の製造方法
US4614021A (en) * 1985-03-29 1986-09-30 Motorola, Inc. Pillar via process
JPS61258453A (ja) * 1985-05-13 1986-11-15 Toshiba Corp 半導体装置の製造方法
JPS63161646A (ja) * 1986-12-25 1988-07-05 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US4888665A (en) * 1988-02-19 1989-12-19 Microelectronics And Computer Technology Corporation Customizable circuitry

Also Published As

Publication number Publication date
US5248854A (en) 1993-09-28
JPH02265243A (ja) 1990-10-30
DE69022874D1 (de) 1995-11-16
EP0394722A3 (de) 1992-01-08
EP0394722B1 (de) 1995-10-11
EP0394722A2 (de) 1990-10-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee