DE69023456T2 - Bitdekodierungsschema für Speichermatrizen. - Google Patents
Bitdekodierungsschema für Speichermatrizen.Info
- Publication number
- DE69023456T2 DE69023456T2 DE69023456T DE69023456T DE69023456T2 DE 69023456 T2 DE69023456 T2 DE 69023456T2 DE 69023456 T DE69023456 T DE 69023456T DE 69023456 T DE69023456 T DE 69023456T DE 69023456 T2 DE69023456 T2 DE 69023456T2
- Authority
- DE
- Germany
- Prior art keywords
- memory arrays
- decoding scheme
- bit decoding
- bit
- scheme
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/418—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US42879489A | 1989-10-30 | 1989-10-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69023456D1 DE69023456D1 (de) | 1995-12-14 |
DE69023456T2 true DE69023456T2 (de) | 1996-06-20 |
Family
ID=23700427
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69023456T Expired - Fee Related DE69023456T2 (de) | 1989-10-30 | 1990-09-21 | Bitdekodierungsschema für Speichermatrizen. |
Country Status (4)
Country | Link |
---|---|
US (1) | US5317541A (de) |
EP (1) | EP0426597B1 (de) |
JP (1) | JPH0772993B2 (de) |
DE (1) | DE69023456T2 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5995016A (en) * | 1996-12-17 | 1999-11-30 | Rambus Inc. | Method and apparatus for N choose M device selection |
US6195398B1 (en) | 1997-12-19 | 2001-02-27 | Stmicroelectronics, Inc. | Method and apparatus for coding and communicating data in noisy environment |
US7247531B2 (en) * | 2004-04-30 | 2007-07-24 | Hewlett-Packard Development Company, L.P. | Field-effect-transistor multiplexing/demultiplexing architectures and methods of forming the same |
US9117499B2 (en) | 2012-10-25 | 2015-08-25 | Elwha Llc | Bipolar logic gates on MOS-based memory chips |
Family Cites Families (60)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3541353A (en) * | 1967-09-13 | 1970-11-17 | Motorola Inc | Mosfet digital gate |
US3614467A (en) * | 1970-06-22 | 1971-10-19 | Cogar Corp | Nonsaturated logic circuits compatible with ttl and dtl circuits |
US3942162A (en) * | 1974-07-01 | 1976-03-02 | Motorola, Inc. | Pre-conditioning circuits for MOS integrated circuits |
FR2304991A1 (fr) * | 1975-03-15 | 1976-10-15 | Ibm | Agencement de circuits pour memoire semi-conductrice et son procede de fonctionnement |
DE2557165C3 (de) * | 1975-12-18 | 1979-01-18 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Decoderschaltung und ihre Anordnung zur Integrierung auf einem Halbleiterbaustein |
US4104735A (en) * | 1976-09-15 | 1978-08-01 | Siemens Aktiengesellschaft | Arrangement for addressing a MOS store |
US4112314A (en) * | 1977-08-26 | 1978-09-05 | International Business Machines Corporation | Logical current switch |
JPS5481046A (en) * | 1977-12-12 | 1979-06-28 | Fujitsu Ltd | Decoder circuit |
JPS5484936A (en) * | 1977-12-20 | 1979-07-06 | Fujitsu Ltd | Decoder circuit |
US4330851A (en) * | 1980-03-21 | 1982-05-18 | Texas Instruments Incorporated | Dynamic decoder input for semiconductor memory |
JPS573289A (en) * | 1980-06-04 | 1982-01-08 | Hitachi Ltd | Semiconductor storing circuit device |
JPS57130286A (en) * | 1981-02-06 | 1982-08-12 | Fujitsu Ltd | Static semiconductor memory |
DE3274039D1 (en) * | 1981-02-25 | 1986-12-04 | Toshiba Kk | Complementary mosfet logic circuit |
US4739497A (en) * | 1981-05-29 | 1988-04-19 | Hitachi, Ltd. | Semiconductor memory |
JPS589285A (ja) * | 1981-07-08 | 1983-01-19 | Toshiba Corp | 半導体装置 |
JPS58169958A (ja) * | 1982-03-31 | 1983-10-06 | Fujitsu Ltd | Misスタテイツク・ランダムアクセスメモリ |
US4604533A (en) * | 1982-12-28 | 1986-08-05 | Tokyo Shibaura Denki Kabushiki Kaisha | Sense amplifier |
US4514829A (en) * | 1982-12-30 | 1985-04-30 | International Business Machines Corporation | Word line decoder and driver circuits for high density semiconductor memory |
JPS59178685A (ja) * | 1983-03-30 | 1984-10-09 | Toshiba Corp | 半導体記憶回路 |
JPS59229784A (ja) * | 1983-06-10 | 1984-12-24 | Hitachi Ltd | バイポ−ラ型ram |
JPH0693626B2 (ja) * | 1983-07-25 | 1994-11-16 | 株式会社日立製作所 | 半導体集積回路装置 |
JPS6043295A (ja) * | 1983-08-17 | 1985-03-07 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPH0616585B2 (ja) * | 1983-12-16 | 1994-03-02 | 株式会社日立製作所 | バツフア回路 |
JPH0795395B2 (ja) * | 1984-02-13 | 1995-10-11 | 株式会社日立製作所 | 半導体集積回路 |
JPS60234292A (ja) * | 1984-05-07 | 1985-11-20 | Hitachi Ltd | Mosスタテイツク型ram |
EP0162934B1 (de) * | 1984-05-14 | 1989-11-08 | Ibm Deutschland Gmbh | Halbleiterspeicher |
US4598390A (en) * | 1984-06-25 | 1986-07-01 | International Business Machines Corporation | Random access memory RAM employing complementary transistor switch (CTS) memory cells |
US4578779A (en) * | 1984-06-25 | 1986-03-25 | International Business Machines Corporation | Voltage mode operation scheme for bipolar arrays |
US4596002A (en) * | 1984-06-25 | 1986-06-17 | International Business Machines Corporation | Random access memory RAM employing complementary transistor switch (CTS) memory cells |
US4616146A (en) * | 1984-09-04 | 1986-10-07 | Motorola, Inc. | BI-CMOS driver circuit |
US4675846A (en) * | 1984-12-17 | 1987-06-23 | International Business Machines Corporation | Random access memory |
US4636983A (en) * | 1984-12-20 | 1987-01-13 | Cypress Semiconductor Corp. | Memory array biasing circuit for high speed CMOS device |
US4639898A (en) * | 1984-12-21 | 1987-01-27 | Rca Corporation | Bit-line pull-up circuit |
US4730279A (en) * | 1985-03-30 | 1988-03-08 | Kabushiki Kaisha Toshiba | Static semiconductor memory device |
US4636990A (en) * | 1985-05-31 | 1987-01-13 | International Business Machines Corporation | Three state select circuit for use in a data processing system or the like |
JP2532831B2 (ja) * | 1985-06-03 | 1996-09-11 | 日本電信電話株式会社 | メモリ回路 |
US4658381A (en) * | 1985-08-05 | 1987-04-14 | Motorola, Inc. | Bit line precharge on a column address change |
JPS6235191A (ja) * | 1985-08-06 | 1987-02-16 | 三井造船株式会社 | 上澄液排出用ジャバラホースの製造方法 |
US4740921A (en) * | 1985-10-04 | 1988-04-26 | Motorola, Inc. | Precharge of a dram data line to an intermediate voltage |
US4638186A (en) * | 1985-12-02 | 1987-01-20 | Motorola, Inc. | BIMOS logic gate |
US4678940A (en) * | 1986-01-08 | 1987-07-07 | Advanced Micro Devices, Inc. | TTL compatible merged bipolar/CMOS output buffer circuits |
US4649295A (en) * | 1986-01-13 | 1987-03-10 | Motorola, Inc. | BIMOS logic gate |
US4668879A (en) * | 1986-02-10 | 1987-05-26 | International Business Machines Corporation | Dotted "or" function for current controlled gates |
JPH0640439B2 (ja) * | 1986-02-17 | 1994-05-25 | 日本電気株式会社 | 半導体記憶装置 |
JPS62221219A (ja) * | 1986-03-22 | 1987-09-29 | Toshiba Corp | 論理回路 |
US4701642A (en) * | 1986-04-28 | 1987-10-20 | International Business Machines Corporation | BICMOS binary logic circuits |
US4752913A (en) * | 1986-04-30 | 1988-06-21 | International Business Machines Corporation | Random access memory employing complementary transistor switch (CTS) memory cells |
JPS6382122A (ja) * | 1986-09-26 | 1988-04-12 | Toshiba Corp | 論理回路 |
US4728827A (en) * | 1986-12-03 | 1988-03-01 | Advanced Micro Devices, Inc. | Static PLA or ROM circuit with self-generated precharge |
JP2901973B2 (ja) * | 1987-04-30 | 1999-06-07 | 株式会社日立製作所 | 半導体集積回路装置 |
US4825413A (en) * | 1987-02-24 | 1989-04-25 | Texas Instruments Incorporated | Bipolar-CMOS static ram memory device |
US4746817A (en) * | 1987-03-16 | 1988-05-24 | International Business Machines Corporation | BIFET logic circuit |
JPS6425394A (en) * | 1987-07-21 | 1989-01-27 | Mitsubishi Electric Corp | Nonvolatile semiconductor memory device |
JPS6482384A (en) * | 1987-09-24 | 1989-03-28 | Hitachi Ltd | Semiconductor integrated circuit device |
JPH01144291A (ja) * | 1987-11-20 | 1989-06-06 | Internatl Business Mach Corp <Ibm> | スタテイツク・ランダム・アクセス・メモリ |
DE3788132T2 (de) * | 1987-12-01 | 1994-05-11 | Ibm | Logische Schaltkreisfamilie von Multibasis-bi-CMOS. |
US4831285A (en) * | 1988-01-19 | 1989-05-16 | National Semiconductor Corporation | Self precharging static programmable logic array |
US4866674A (en) * | 1988-02-16 | 1989-09-12 | Texas Instruments Incorporated | Bitline pull-up circuit for a BiCMOS read/write memory |
US4862421A (en) * | 1988-02-16 | 1989-08-29 | Texas Instruments Incorporated | Sensing and decoding scheme for a BiCMOS read/write memory |
US4922461A (en) * | 1988-03-30 | 1990-05-01 | Kabushiki Kaisha Toshiba | Static random access memory with address transition detector |
-
1990
- 1990-09-21 DE DE69023456T patent/DE69023456T2/de not_active Expired - Fee Related
- 1990-09-21 EP EP90480144A patent/EP0426597B1/de not_active Expired - Lifetime
- 1990-10-19 JP JP2279499A patent/JPH0772993B2/ja not_active Expired - Lifetime
-
1991
- 1991-07-08 US US07/728,021 patent/US5317541A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH03144997A (ja) | 1991-06-20 |
EP0426597A2 (de) | 1991-05-08 |
EP0426597B1 (de) | 1995-11-08 |
JPH0772993B2 (ja) | 1995-08-02 |
DE69023456D1 (de) | 1995-12-14 |
EP0426597A3 (de) | 1991-07-24 |
US5317541A (en) | 1994-05-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
NO900814D0 (no) | Borkrone. | |
NO905093D0 (no) | Borkrone. | |
NO904132D0 (no) | Borkrone. | |
DE3885408T2 (de) | Nichtflüchtige Speicherzelle. | |
DE3587400T2 (de) | Datenspeicherungsanordnung. | |
DE3882278T2 (de) | MOS-Speicher. | |
DE3485038D1 (de) | Mos-speicher. | |
DE69019551D1 (de) | Speicheranordnungen. | |
NO905094L (no) | Borkrone. | |
DE3885594T2 (de) | Speicherprüfgerät. | |
DE3854037D1 (de) | Speicheraddressierungsfehlererkennung. | |
DE3869158D1 (de) | Speicher-leseschaltung. | |
DE69020764T2 (de) | Speicheradressierung. | |
DE3783100T2 (de) | Festwertspeicheranordnung. | |
DE3585811D1 (de) | Direktzugriffsspeicher. | |
DE3680829D1 (de) | Festwertspeicheranordnung. | |
DE69023455T2 (de) | Wortdekodierungsschema für Speichermatrizen. | |
NO900662D0 (no) | Borkrone. | |
FI884979A (fi) | Muistibitin ennakointipiiri | |
DE69023456D1 (de) | Bitdekodierungsschema für Speichermatrizen. | |
DE3854005D1 (de) | Speicherzelle. | |
DE3778389D1 (de) | Magnetisch-optisches gedaechtnismedium. | |
DE3850608D1 (de) | Cache-Speicheranordnung. | |
DE3583283D1 (de) | Speicherbusarchitektur. | |
NO871037L (no) | Borkrone. |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |