DE69028939T2 - Verfahren zum Ätzen von Kontaktlöchern mit abgeschrägten Flanken - Google Patents

Verfahren zum Ätzen von Kontaktlöchern mit abgeschrägten Flanken

Info

Publication number
DE69028939T2
DE69028939T2 DE69028939T DE69028939T DE69028939T2 DE 69028939 T2 DE69028939 T2 DE 69028939T2 DE 69028939 T DE69028939 T DE 69028939T DE 69028939 T DE69028939 T DE 69028939T DE 69028939 T2 DE69028939 T2 DE 69028939T2
Authority
DE
Germany
Prior art keywords
contact holes
etching contact
sloping flanks
flanks
sloping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69028939T
Other languages
English (en)
Other versions
DE69028939D1 (de
Inventor
David Wington Cheung
Norman Edwin Abt
Peter A Mcnally
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of DE69028939D1 publication Critical patent/DE69028939D1/de
Application granted granted Critical
Publication of DE69028939T2 publication Critical patent/DE69028939T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
DE69028939T 1989-03-24 1990-03-15 Verfahren zum Ätzen von Kontaktlöchern mit abgeschrägten Flanken Expired - Lifetime DE69028939T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/328,179 US5354386A (en) 1989-03-24 1989-03-24 Method for plasma etching tapered and stepped vias

Publications (2)

Publication Number Publication Date
DE69028939D1 DE69028939D1 (de) 1996-11-28
DE69028939T2 true DE69028939T2 (de) 1997-05-22

Family

ID=23279859

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69028939T Expired - Lifetime DE69028939T2 (de) 1989-03-24 1990-03-15 Verfahren zum Ätzen von Kontaktlöchern mit abgeschrägten Flanken

Country Status (6)

Country Link
US (1) US5354386A (de)
EP (1) EP0388796B1 (de)
JP (1) JPH02284419A (de)
KR (1) KR900015269A (de)
CA (1) CA1315022C (de)
DE (1) DE69028939T2 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2787646B2 (ja) 1992-11-27 1998-08-20 三菱電機株式会社 半導体装置の製造方法
US5739068A (en) * 1995-02-22 1998-04-14 Micron Technology, Inc. Semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material
US5854140A (en) * 1996-12-13 1998-12-29 Siemens Aktiengesellschaft Method of making an aluminum contact
EP0871213A3 (de) * 1997-03-27 1999-03-03 Siemens Aktiengesellschaft Verfahren zur Bildung von Kontaktbohrungen mit variablem Seitenwandprofil
US6165375A (en) * 1997-09-23 2000-12-26 Cypress Semiconductor Corporation Plasma etching method
CA2238128A1 (en) * 1998-05-20 1999-11-20 Hualon Microelectronics Corporation 3-step etching for contact window
EP0991123A1 (de) * 1998-10-01 2000-04-05 EM Microelectronic-Marin SA Mikrostruktur mit einer magnetischen Antenne oder einem magnetischen Detector
US6372634B1 (en) 1999-06-15 2002-04-16 Cypress Semiconductor Corp. Plasma etch chemistry and method of improving etch control
US6322716B1 (en) 1999-08-30 2001-11-27 Cypress Semiconductor Corp. Method for conditioning a plasma etch chamber
DE10059836A1 (de) * 2000-12-01 2002-06-13 Infineon Technologies Ag Verfahren zur Strukturierung dielektrischer Schichten
US7390755B1 (en) 2002-03-26 2008-06-24 Novellus Systems, Inc. Methods for post etch cleans
US7238609B2 (en) * 2003-02-26 2007-07-03 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor device
US7060624B2 (en) * 2003-08-13 2006-06-13 International Business Machines Corporation Deep filled vias
US7288484B1 (en) 2004-07-13 2007-10-30 Novellus Systems, Inc. Photoresist strip method for low-k dielectrics
DE102004057536B3 (de) * 2004-11-29 2006-05-11 Infineon Technologies Ag Verfahren zum Herstellen von Öffnungen mit wenigstens zwei voneinander unterschiedlichen Strukturgrößen in einer Schicht
US7687407B2 (en) * 2004-12-02 2010-03-30 Texas Instruments Incorporated Method for reducing line edge roughness for conductive features
US8193096B2 (en) 2004-12-13 2012-06-05 Novellus Systems, Inc. High dose implantation strip (HDIS) in H2 base chemistry
US7202176B1 (en) * 2004-12-13 2007-04-10 Novellus Systems, Inc. Enhanced stripping of low-k films using downstream gas mixing
US8129281B1 (en) 2005-05-12 2012-03-06 Novellus Systems, Inc. Plasma based photoresist removal system for cleaning post ash residue
US7740768B1 (en) 2006-10-12 2010-06-22 Novellus Systems, Inc. Simultaneous front side ash and backside clean
US8435895B2 (en) 2007-04-04 2013-05-07 Novellus Systems, Inc. Methods for stripping photoresist and/or cleaning metal regions
US8591661B2 (en) 2009-12-11 2013-11-26 Novellus Systems, Inc. Low damage photoresist strip method for low-K dielectrics
WO2011072061A2 (en) 2009-12-11 2011-06-16 Novellus Systems, Inc. Enhanced passivation process to protect silicon prior to high dose implant strip
US20110143548A1 (en) 2009-12-11 2011-06-16 David Cheung Ultra low silicon loss high dose implant strip
KR101636998B1 (ko) 2010-02-12 2016-07-08 삼성디스플레이 주식회사 박막 트랜지스터 및 그 제조 방법
WO2012098759A1 (ja) * 2011-01-17 2012-07-26 住友電気工業株式会社 炭化珪素半導体装置の製造方法
US8871105B2 (en) * 2011-05-12 2014-10-28 Lam Research Corporation Method for achieving smooth side walls after Bosch etch process
FR2975826A1 (fr) * 2011-05-27 2012-11-30 St Microelectronics Crolles 2 Procede de formation d'un trou ou d'une tranchee ayant un profil evase
US9613825B2 (en) 2011-08-26 2017-04-04 Novellus Systems, Inc. Photoresist strip processes for improved device integrity
US9514954B2 (en) 2014-06-10 2016-12-06 Lam Research Corporation Peroxide-vapor treatment for enhancing photoresist-strip performance and modifying organic films
US9917027B2 (en) * 2015-12-30 2018-03-13 Globalfoundries Singapore Pte. Ltd. Integrated circuits with aluminum via structures and methods for fabricating the same
US11018134B2 (en) 2017-09-26 2021-05-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for manufacturing the same
CN112164695B (zh) * 2020-09-14 2022-05-10 长江存储科技有限责任公司 三维存储器的制作方法及三维存储器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59130426A (ja) * 1983-01-17 1984-07-27 Toshiba Corp 半導体装置の製造方法
US4451326A (en) * 1983-09-07 1984-05-29 Advanced Micro Devices, Inc. Method for interconnecting metallic layers
US4698132A (en) * 1986-09-30 1987-10-06 Rca Corporation Method of forming tapered contact openings
US4698128A (en) * 1986-11-17 1987-10-06 Motorola, Inc. Sloped contact etch process
JPH04293230A (ja) * 1991-03-22 1992-10-16 Sanyo Electric Co Ltd コンタクトホールの形成方法

Also Published As

Publication number Publication date
EP0388796B1 (de) 1996-10-23
EP0388796A2 (de) 1990-09-26
KR900015269A (ko) 1990-10-26
CA1315022C (en) 1993-03-23
US5354386A (en) 1994-10-11
DE69028939D1 (de) 1996-11-28
EP0388796A3 (de) 1991-01-02
JPH02284419A (ja) 1990-11-21

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