DE69030640D1 - Multiprozessorarbitrierung in für Einzelprozessor bestimmten Arbitrierungsschemas - Google Patents

Multiprozessorarbitrierung in für Einzelprozessor bestimmten Arbitrierungsschemas

Info

Publication number
DE69030640D1
DE69030640D1 DE69030640T DE69030640T DE69030640D1 DE 69030640 D1 DE69030640 D1 DE 69030640D1 DE 69030640 T DE69030640 T DE 69030640T DE 69030640 T DE69030640 T DE 69030640T DE 69030640 D1 DE69030640 D1 DE 69030640D1
Authority
DE
Germany
Prior art keywords
arbitration
multiprocessor
single processor
schemes
arbitration schemes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69030640T
Other languages
English (en)
Other versions
DE69030640T2 (de
Inventor
Kenneth A Jansen
Montgomery C Mcgraw
David A Miller
Paul R Culley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Publication of DE69030640D1 publication Critical patent/DE69030640D1/de
Application granted granted Critical
Publication of DE69030640T2 publication Critical patent/DE69030640T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
DE69030640T 1989-11-03 1990-10-29 Multiprozessorarbitrierung in für Einzelprozessor bestimmten Arbitrierungsschemas Expired - Lifetime DE69030640T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US43174689A 1989-11-03 1989-11-03

Publications (2)

Publication Number Publication Date
DE69030640D1 true DE69030640D1 (de) 1997-06-12
DE69030640T2 DE69030640T2 (de) 1997-11-06

Family

ID=23713253

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69030640T Expired - Lifetime DE69030640T2 (de) 1989-11-03 1990-10-29 Multiprozessorarbitrierung in für Einzelprozessor bestimmten Arbitrierungsschemas

Country Status (4)

Country Link
US (1) US5392436A (de)
EP (1) EP0426413B1 (de)
CA (1) CA2029198A1 (de)
DE (1) DE69030640T2 (de)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2774862B2 (ja) * 1990-07-16 1998-07-09 株式会社日立製作所 Dma制御装置および情報処理装置
JP2854474B2 (ja) * 1992-09-29 1999-02-03 三菱電機株式会社 バス使用要求調停装置
US5845310A (en) * 1993-12-15 1998-12-01 Hewlett-Packard Co. System and methods for performing cache latency diagnostics in scalable parallel processing architectures including calculating CPU idle time and counting number of cache misses
JP2644185B2 (ja) * 1994-06-27 1997-08-25 甲府日本電気株式会社 データ処理装置
JPH10502196A (ja) * 1994-06-29 1998-02-24 インテル・コーポレーション アップグレード可能なマルチプロセッサ・コンピュータシステムでシステムバス所有権を指示するプロセッサ
US5524235A (en) * 1994-10-14 1996-06-04 Compaq Computer Corporation System for arbitrating access to memory with dynamic priority assignment
US5923859A (en) * 1995-04-13 1999-07-13 Compaq Computer Corporation Dual arbiters for arbitrating access to a first and second bus in a computer system having bus masters on each bus
US5787264A (en) * 1995-05-08 1998-07-28 Apple Computer, Inc. Method and apparatus for arbitrating access to a shared bus
KR0144022B1 (ko) * 1995-05-15 1998-08-17 김주용 엘알유에 의한 중재기
US5572686A (en) * 1995-06-05 1996-11-05 Apple Computer, Inc. Bus arbitration scheme with priority switching and timer
JPH08339346A (ja) * 1995-06-09 1996-12-24 Toshiba Corp バスアービタ
US5872992A (en) * 1995-08-24 1999-02-16 Motorola, Inc. System and method for avoiding bus contention on a multiplexed bus by providing a time period subsequent to a read operation
EP0770961A3 (de) * 1995-10-24 2001-04-11 Konica Corporation Speicherzugriffsystem
US5943483A (en) * 1995-12-11 1999-08-24 Lsi Logic Corporation Method and apparatus for controlling access to a bus in a data processing system
US5745913A (en) * 1996-08-05 1998-04-28 Exponential Technology, Inc. Multi-processor DRAM controller that prioritizes row-miss requests to stale banks
US6076127A (en) * 1996-11-06 2000-06-13 International Business Machines Corporation Configuration of a single point bus arbitration scheme using on-chip arbiters
US5805836A (en) * 1996-12-10 1998-09-08 International Business Machines Corporation Method and apparatus for equalizing grants of a data bus to primary and secondary devices
US5953502A (en) * 1997-02-13 1999-09-14 Helbig, Sr.; Walter A Method and apparatus for enhancing computer system security
US5862353A (en) * 1997-03-25 1999-01-19 International Business Machines Corporation Systems and methods for dynamically controlling a bus
US6016528A (en) * 1997-10-29 2000-01-18 Vlsi Technology, Inc. Priority arbitration system providing low latency and guaranteed access for devices
US6026459A (en) * 1998-02-03 2000-02-15 Src Computers, Inc. System and method for dynamic priority conflict resolution in a multi-processor computer system having shared memory resources
US6501765B1 (en) * 1998-09-01 2002-12-31 At&T Corp. Distributed method and apparatus for allocating a communication medium
US6442631B1 (en) 1999-05-07 2002-08-27 Compaq Information Technologies Group, L.P. Allocating system resources based upon priority
US6564326B2 (en) 1999-07-06 2003-05-13 Walter A. Helbig, Sr. Method and apparatus for enhancing computer system security
US6738845B1 (en) 1999-11-05 2004-05-18 Analog Devices, Inc. Bus architecture and shared bus arbitration method for a communication device
WO2001035210A2 (en) * 1999-11-05 2001-05-17 Analog Devices, Inc. Bus architecture and shared bus arbitration method for a communication processor
IT1320466B1 (it) * 2000-06-29 2003-11-26 Cselt Centro Studi Lab Telecom Procedimento e apparecchiuatura per l'arbitrio di processi concorrenti in sistemi multiprocessore.
JP2004199187A (ja) * 2002-12-16 2004-07-15 Matsushita Electric Ind Co Ltd Cpu内蔵lsi
WO2006082538A1 (en) * 2005-02-02 2006-08-10 Koninklijke Philips Electronics N.V. Data processing system and method for accessing an electronic resource
US7890686B2 (en) * 2005-10-17 2011-02-15 Src Computers, Inc. Dynamic priority conflict resolution in a multi-processor computer system having shared resources
FR2894696A1 (fr) * 2005-12-14 2007-06-15 Thomson Licensing Sas Procede d'acces a un bus de transmission de donnees, dispositif et systeme correspondant
US8688933B2 (en) 2006-08-31 2014-04-01 Hewlett-Packard Development Company, L.P. Firmware component modification
US10496577B2 (en) 2017-02-09 2019-12-03 Hewlett Packard Enterprise Development Lp Distribution of master device tasks among bus queues
KR20200056548A (ko) * 2018-11-14 2020-05-25 에스케이하이닉스 주식회사 캐시 시스템을 갖는 메모리 시스템 및 메모리 시스템에서의 캐싱 동작 제어방법

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5812611B2 (ja) * 1975-10-15 1983-03-09 株式会社東芝 デ−タテンソウセイギヨホウシキ
US4257095A (en) * 1978-06-30 1981-03-17 Intel Corporation System bus arbitration, circuitry and methodology
FR2474199B1 (fr) * 1980-01-21 1986-05-16 Bull Sa Dispositif pour superposer les phases successives du transfert des informations entre plusieurs unites d'un systeme de traitement de l'information
US4320457A (en) * 1980-02-04 1982-03-16 General Automation, Inc. Communication bus acquisition circuit
JPS5856746B2 (ja) * 1980-04-15 1983-12-16 日本ステンレス株式会社 プレス成形性および耐食性の良好なオ−ステナイト系ステンレス鋼
US4402040A (en) * 1980-09-24 1983-08-30 Raytheon Company Distributed bus arbitration method and apparatus
US4375639A (en) * 1981-01-12 1983-03-01 Harris Corporation Synchronous bus arbiter
JPS5848130A (ja) * 1981-09-17 1983-03-22 Mitsubishi Electric Corp バスプライオリテイ制御装置
US4488218A (en) * 1982-01-07 1984-12-11 At&T Bell Laboratories Dynamic priority queue occupancy scheme for access to a demand-shared bus
JPS58222361A (ja) * 1982-06-18 1983-12-24 Fujitsu Ltd デ−タ処理システムにおけるアクセス要求の優先順位決定制御方式
US4494192A (en) * 1982-07-21 1985-01-15 Sperry Corporation High speed bus architecture
JPS59111561A (ja) * 1982-12-17 1984-06-27 Hitachi Ltd 複合プロセツサ・システムのアクセス制御方式
US4602327A (en) * 1983-07-28 1986-07-22 Motorola, Inc. Bus master capable of relinquishing bus on request and retrying bus cycle
US4620278A (en) * 1983-08-29 1986-10-28 Sperry Corporation Distributed bus arbitration according each bus user the ability to inhibit all new requests to arbitrate the bus, or to cancel its own pending request, and according the highest priority user the ability to stop the bus
GB2138183B (en) * 1984-01-28 1986-09-24 Standard Telephones Cables Ltd Multi-procesor system
US4745548A (en) * 1984-02-17 1988-05-17 American Telephone And Telegraph Company, At&T Bell Laboratories Decentralized bus arbitration using distributed arbiters having circuitry for latching lockout signals gated from higher priority arbiters
US4639859A (en) * 1984-05-24 1987-01-27 Rca Corporation Priority arbitration logic for a multi-master bus system
SE445861B (sv) * 1984-12-12 1986-07-21 Ellemtel Utvecklings Ab Prioritetsfordelningsanordning for datorer
US4837682A (en) * 1987-04-07 1989-06-06 Glen Culler & Associates Bus arbitration system and method
JPS63284660A (ja) * 1987-05-16 1988-11-21 Nec Corp プロセッサ間通信方式
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters

Also Published As

Publication number Publication date
EP0426413A2 (de) 1991-05-08
EP0426413A3 (en) 1991-12-04
US5392436A (en) 1995-02-21
EP0426413B1 (de) 1997-05-07
DE69030640T2 (de) 1997-11-06
CA2029198A1 (en) 1991-05-04

Similar Documents

Publication Publication Date Title
DE69030640T2 (de) Multiprozessorarbitrierung in für Einzelprozessor bestimmten Arbitrierungsschemas
DE68925763D1 (de) Verbindungs- und Zugriffsarbitrierungsanordnung für Multiprozessorsystem
DE3856015D1 (de) Berechnungseinrichtung für Parallelprozessoren
DE3781694D1 (de) Virtuelle prozessortechniken in einem feldmultiprozessor.
DE68926783D1 (de) Paralleler datenprozessor
DE69027253D1 (de) Multiprozessor-Cachespeichersystem
DE69032337T2 (de) Multiprozessorsystem verwendendes Datenbasisverarbeitungssystem
DE68925646T2 (de) Pipeline-multiprozessorsystem
DE68926043T2 (de) Mehrprozessor-Computersystem
DE69224571D1 (de) Mehrprozessorrechnersystem
DE68929215D1 (de) Datenprozessor
DE69033384D1 (de) Entwicklungsgerät
DE69007732D1 (de) Befestigungsvorrichtung für Computerperipherien.
DK0570359T3 (da) Heuristisk processor
DE69027104D1 (de) Prozessor mit mehreren mikroprogrammierten Ausführungseinheiten
DE68927513T2 (de) Prozessor für Prozessregelung
DE69030066D1 (de) Rechner ausgestattet mit mehreren Prozessoren
DE68927202T2 (de) Paralleler Prozessor
ES531078A0 (es) Perfeccionamientos en las instalaciones de ordenadores.
MX161700A (es) Mejoras en procesador asociativo
KR920013153U (ko) 다중처리기 시스템에서의 데이터버스 중재기
DE68925991D1 (de) Unparteiisches Arbitrierungsschema
BR6900534U (pt) Disposicao introduzida em bandeja
KR910012474U (ko) 셀프코드 아비터
BR6900666U (pt) Multiprocessador de graos

Legal Events

Date Code Title Description
8364 No opposition during term of opposition