DE69031183D1 - Verfahren und Anordnung zur Kontrolle der Umwandlung virtueller Adressen in physikalische Adressen in einem Computersystem - Google Patents

Verfahren und Anordnung zur Kontrolle der Umwandlung virtueller Adressen in physikalische Adressen in einem Computersystem

Info

Publication number
DE69031183D1
DE69031183D1 DE69031183T DE69031183T DE69031183D1 DE 69031183 D1 DE69031183 D1 DE 69031183D1 DE 69031183 T DE69031183 T DE 69031183T DE 69031183 T DE69031183 T DE 69031183T DE 69031183 D1 DE69031183 D1 DE 69031183D1
Authority
DE
Germany
Prior art keywords
translation buffer
memory
virtual
physical
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69031183T
Other languages
English (en)
Other versions
DE69031183T2 (de
Inventor
Ricky C Hetherington
David A Webb
David B Fite
John E Murray
Tryggve Fossum
Dwight P Manley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of DE69031183D1 publication Critical patent/DE69031183D1/de
Publication of DE69031183T2 publication Critical patent/DE69031183T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855Overlapped cache accessing, e.g. pipeline
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
DE69031183T 1989-02-03 1990-01-30 Verfahren und Anordnung zur Kontrolle der Umwandlung virtueller Adressen in physikalische Adressen in einem Computersystem Expired - Lifetime DE69031183T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US30654489A 1989-02-03 1989-02-03
AU53950/90A AU632558B2 (en) 1989-02-03 1990-04-27 Method and apparatus for controlling the conversion of virtual to physical memory addresses in a digital computer system

Publications (2)

Publication Number Publication Date
DE69031183D1 true DE69031183D1 (de) 1997-09-11
DE69031183T2 DE69031183T2 (de) 1998-03-12

Family

ID=25630274

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69031183T Expired - Lifetime DE69031183T2 (de) 1989-02-03 1990-01-30 Verfahren und Anordnung zur Kontrolle der Umwandlung virtueller Adressen in physikalische Adressen in einem Computersystem

Country Status (7)

Country Link
US (1) US5349651A (de)
EP (1) EP0381447B1 (de)
JP (1) JPH02232753A (de)
AT (1) ATE156609T1 (de)
AU (1) AU632558B2 (de)
CA (1) CA1325288C (de)
DE (1) DE69031183T2 (de)

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US6061749A (en) * 1997-04-30 2000-05-09 Canon Kabushiki Kaisha Transformation of a first dataword received from a FIFO into an input register and subsequent dataword from the FIFO into a normalized output dataword
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US6233668B1 (en) 1999-10-27 2001-05-15 Compaq Computer Corporation Concurrent page tables
US6628294B1 (en) 1999-12-31 2003-09-30 Intel Corporation Prefetching of virtual-to-physical address translation for display data
US6615300B1 (en) * 2000-06-19 2003-09-02 Transmeta Corporation Fast look-up of indirect branch destination in a dynamic translation system
US9131899B2 (en) 2011-07-06 2015-09-15 Apple Inc. Efficient handling of misaligned loads and stores
US7404064B2 (en) * 2004-04-07 2008-07-22 Stmicroelectronics S.A. Method and device for calculating addresses of a segmented program memory
US10621092B2 (en) 2008-11-24 2020-04-14 Intel Corporation Merging level cache and data cache units having indicator bits related to speculative execution
US9672019B2 (en) 2008-11-24 2017-06-06 Intel Corporation Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads
US8775153B2 (en) * 2009-12-23 2014-07-08 Intel Corporation Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment
US9921967B2 (en) * 2011-07-26 2018-03-20 Intel Corporation Multi-core shared page miss handler
WO2013048468A1 (en) 2011-09-30 2013-04-04 Intel Corporation Instruction and logic to perform dynamic binary translation
US9292453B2 (en) 2013-02-01 2016-03-22 International Business Machines Corporation Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB)
US9405551B2 (en) 2013-03-12 2016-08-02 Intel Corporation Creating an isolated execution environment in a co-designed processor
US9891936B2 (en) 2013-09-27 2018-02-13 Intel Corporation Method and apparatus for page-level monitoring
US9477611B2 (en) * 2013-10-21 2016-10-25 Marvell World Trade Ltd. Final level cache system and corresponding methods

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Also Published As

Publication number Publication date
EP0381447A2 (de) 1990-08-08
EP0381447B1 (de) 1997-08-06
JPH02232753A (ja) 1990-09-14
AU5395090A (en) 1991-12-19
JPH0564815B2 (de) 1993-09-16
US5349651A (en) 1994-09-20
EP0381447A3 (de) 1992-05-13
AU632558B2 (en) 1993-01-07
DE69031183T2 (de) 1998-03-12
CA1325288C (en) 1993-12-14
ATE156609T1 (de) 1997-08-15

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8328 Change in the person/name/address of the agent

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