DE69031197D1 - Plazierungs-Optimierungsverfahren /-vorrichtung für den Entwurf von Halbleiterbausteinen - Google Patents

Plazierungs-Optimierungsverfahren /-vorrichtung für den Entwurf von Halbleiterbausteinen

Info

Publication number
DE69031197D1
DE69031197D1 DE69031197T DE69031197T DE69031197D1 DE 69031197 D1 DE69031197 D1 DE 69031197D1 DE 69031197 T DE69031197 T DE 69031197T DE 69031197 T DE69031197 T DE 69031197T DE 69031197 D1 DE69031197 D1 DE 69031197D1
Authority
DE
Germany
Prior art keywords
design
semiconductor devices
optimization method
placement optimization
placement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69031197T
Other languages
English (en)
Inventor
Hiroshi Date
Terumine Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE69031197D1 publication Critical patent/DE69031197D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/10—Interfaces, programming languages or software development kits, e.g. for simulating neural networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S706/00—Data processing: artificial intelligence
    • Y10S706/902—Application using ai with detail of the ai system
    • Y10S706/919—Designing, planning, programming, CAD, CASE
    • Y10S706/921—Layout, e.g. circuit, construction
DE69031197T 1989-06-08 1990-05-31 Plazierungs-Optimierungsverfahren /-vorrichtung für den Entwurf von Halbleiterbausteinen Expired - Lifetime DE69031197D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14412389A JP2863550B2 (ja) 1989-06-08 1989-06-08 配置最適化方法及び配置最適化装置と回路設計装置

Publications (1)

Publication Number Publication Date
DE69031197D1 true DE69031197D1 (de) 1997-09-11

Family

ID=15354731

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69031197T Expired - Lifetime DE69031197D1 (de) 1989-06-08 1990-05-31 Plazierungs-Optimierungsverfahren /-vorrichtung für den Entwurf von Halbleiterbausteinen

Country Status (5)

Country Link
US (1) US5200908A (de)
EP (1) EP0401687B1 (de)
JP (1) JP2863550B2 (de)
KR (1) KR0157415B1 (de)
DE (1) DE69031197D1 (de)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0410000A4 (en) * 1989-02-10 1993-09-01 Hitachi, Ltd. Data processing unit for obtaining solution for optimal combination solution and method thereof
US5361214A (en) * 1990-07-09 1994-11-01 Kabushiki Kaisha Toshiba Method for automatically determining wiring routes
JPH04130968A (ja) * 1990-09-21 1992-05-01 Toshiba Corp ニューラルネットワークを用いた配線方式
US5452400A (en) * 1991-08-30 1995-09-19 Mitsubishi Denki Kabushiki Kaisha Method of optimizing a combination using a neural network
JP2887969B2 (ja) * 1991-08-30 1999-05-10 三菱電機株式会社 ニューラルネットワークによる部品配置最適化方法
JPH05128085A (ja) * 1991-11-08 1993-05-25 Toshiba Corp システム制御の学習方法
JP3479538B2 (ja) * 1991-12-26 2003-12-15 テキサス インスツルメンツ インコーポレイテツド 半導体集積回路を製作する方法
JP3220250B2 (ja) * 1992-01-09 2001-10-22 株式会社東芝 セル自動配置方法
JP3201156B2 (ja) * 1993-08-30 2001-08-20 トヨタ自動車株式会社 設計を支援する方法と装置
JP3192057B2 (ja) * 1994-03-18 2001-07-23 富士通株式会社 配線プログラム生成方法及びその装置
US5691913A (en) * 1994-03-28 1997-11-25 Matsushita Electric Ind. Co. Layout designing apparatus for circuit boards
US6493658B1 (en) 1994-04-19 2002-12-10 Lsi Logic Corporation Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithms
US5557533A (en) * 1994-04-19 1996-09-17 Lsi Logic Corporation Cell placement alteration apparatus for integrated circuit chip physical design automation system
US6155725A (en) * 1994-04-19 2000-12-05 Lsi Logic Corporation Cell placement representation and transposition for integrated circuit physical design automation system
US5963975A (en) * 1994-04-19 1999-10-05 Lsi Logic Corporation Single chip integrated circuit distributed shared memory (DSM) and communications nodes
US5914887A (en) * 1994-04-19 1999-06-22 Lsi Logic Corporation Congestion based cost factor computing apparatus for integrated circuit physical design automation system
US5815403A (en) * 1994-04-19 1998-09-29 Lsi Logic Corporation Fail-safe distributive processing method for producing a highest fitness cell placement for an integrated circuit chip
US5875117A (en) * 1994-04-19 1999-02-23 Lsi Logic Corporation Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system
US5495419A (en) * 1994-04-19 1996-02-27 Lsi Logic Corporation Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing
US5535134A (en) * 1994-06-03 1996-07-09 International Business Machines Corporation Object placement aid
US5590063A (en) * 1994-07-05 1996-12-31 Motorola, Inc. Optimization method using parallel processors
US5740071A (en) * 1995-06-07 1998-04-14 International Business Machines Corporation Method and apparatus for selective shape adjustment of hierarchical designs
US5740067A (en) * 1995-10-19 1998-04-14 International Business Machines Corporation Method for clock skew cost calculation
US5745735A (en) * 1995-10-26 1998-04-28 International Business Machines Corporation Localized simulated annealing
US5971588A (en) * 1996-06-28 1999-10-26 Lsi Logic Corporation Advanced modular cell placement system with optimization of cell neighborhood system
US5831863A (en) * 1996-06-28 1998-11-03 Lsi Logic Corporation Advanced modular cell placement system with wire length driven affinity system
US6026223A (en) * 1996-06-28 2000-02-15 Scepanovic; Ranko Advanced modular cell placement system with overlap remover with minimal noise
US5844811A (en) * 1996-06-28 1998-12-01 Lsi Logic Corporation Advanced modular cell placement system with universal affinity driven discrete placement optimization
US5867398A (en) * 1996-06-28 1999-02-02 Lsi Logic Corporation Advanced modular cell placement system with density driven capacity penalty system
US5870311A (en) * 1996-06-28 1999-02-09 Lsi Logic Corporation Advanced modular cell placement system with fast procedure for finding a levelizing cut point
US5870312A (en) * 1996-06-28 1999-02-09 Lsi Logic Corporation Advanced modular cell placement system with dispersion-driven levelizing system
US5808899A (en) * 1996-06-28 1998-09-15 Lsi Logic Corporation Advanced modular cell placement system with cell placement crystallization
US5914888A (en) * 1996-06-28 1999-06-22 Lsi Logic Corporation Advanced modular cell placement system with coarse overflow remover
US6085032A (en) * 1996-06-28 2000-07-04 Lsi Logic Corporation Advanced modular cell placement system with sinusoidal optimization
US5892688A (en) * 1996-06-28 1999-04-06 Lsi Logic Corporation Advanced modular cell placement system with iterative one dimensional preplacement optimization
US5812740A (en) * 1996-06-28 1998-09-22 Lsi Logic Corporation Advanced modular cell placement system with neighborhood system driven optimization
US5963455A (en) * 1996-06-28 1999-10-05 Lsi Logic Corporation Advanced modular cell placement system with functional sieve optimization technique
US5872718A (en) * 1996-06-28 1999-02-16 Lsi Logic Corporation Advanced modular cell placement system
US6067409A (en) * 1996-06-28 2000-05-23 Lsi Logic Corporation Advanced modular cell placement system
US5835381A (en) * 1996-06-28 1998-11-10 Lsi Logic Corporation Advanced modular cell placement system with minimizing maximal cut driven affinity system
US6030110A (en) * 1996-06-28 2000-02-29 Lsi Logic Corporation Advanced modular cell placement system with median control and increase in resolution
US5980093A (en) * 1996-12-04 1999-11-09 Lsi Logic Corporation Integrated circuit layout routing using multiprocessing
US5953518A (en) * 1997-03-14 1999-09-14 Lsi Logic Corporation Yield improvement techniques through layout optimization
US6993186B1 (en) 1997-12-29 2006-01-31 Glickman Jeff B Energy minimization for classification, pattern recognition, sensor fusion, data compression, network reconstruction and signal processing
US6324436B1 (en) 1998-09-14 2001-11-27 Fujitsu Limited Method for optimizing cost of manufacturing memory arrays
KR100352603B1 (ko) * 1998-12-21 2002-10-19 주식회사 포스코 내화조성물 및 이를 이용한 턴디쉬의 상부노즐
US7342414B2 (en) * 2002-02-01 2008-03-11 California Institute Of Technology Fast router and hardware-assisted fast routing method
JP2003249591A (ja) * 2002-02-26 2003-09-05 Nec Electronics Corp エリアｉｏ型半導体装置の配線基板の設計方法
AU2003259919A1 (en) * 2002-08-21 2004-03-11 California Institute Of Technology Element placement method and apparatus
US7285487B2 (en) * 2003-07-24 2007-10-23 California Institute Of Technology Method and apparatus for network with multilayer metalization
US9061119B2 (en) 2008-05-09 2015-06-23 Edwards Lifesciences Corporation Low profile delivery system for transcatheter heart valve
US10192016B2 (en) * 2017-01-17 2019-01-29 Xilinx, Inc. Neural network based physical synthesis for circuit designs
CN113722853B (zh) * 2021-08-30 2024-03-05 河南大学 一种面向智能计算的群智能进化式工程设计约束优化方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3629843A (en) * 1970-05-11 1971-12-21 Bell Telephone Labor Inc Machine process for assigning interconnected components to locations in a planar matrix
US3702003A (en) * 1970-10-09 1972-10-31 Marathon Oil Co Algorithm to minimize iterative computation in a process for the analysis or design of a physical system
US3681782A (en) * 1970-12-02 1972-08-01 Honeywell Inf Systems Machine process for positioning interconnected components to minimize interconnecting line length
US4580228A (en) * 1983-06-06 1986-04-01 The United States Of America As Represented By The Secretary Of The Army Automated design program for LSI and VLSI circuits
US4593363A (en) * 1983-08-12 1986-06-03 International Business Machines Corporation Simultaneous placement and wiring for VLSI chips
US4577276A (en) * 1983-09-12 1986-03-18 At&T Bell Laboratories Placement of components on circuit substrates
JPS6293760A (ja) * 1985-10-18 1987-04-30 Nec Corp 配置改良装置
US4719591A (en) * 1985-11-07 1988-01-12 American Telephone And Telegraph Company, At&T Bell Labs. Optimization network for the decomposition of signals
US4754408A (en) * 1985-11-21 1988-06-28 International Business Machines Corporation Progressive insertion placement of elements on an integrated circuit
USH354H (en) * 1986-04-04 1987-10-06 The United States Of America As Represented By The Secretary Of The Army Linear algorithm for non-linear interpolation for computer aided designs
JPS62243071A (ja) * 1986-04-16 1987-10-23 Fujitsu Ltd 並列配置改善方式
JPS63121978A (ja) * 1986-11-11 1988-05-26 Fujitsu Ltd 大規模組合せ問題の最適化処理装置

Also Published As

Publication number Publication date
KR0157415B1 (ko) 1998-11-16
JPH0310378A (ja) 1991-01-17
EP0401687A2 (de) 1990-12-12
US5200908A (en) 1993-04-06
JP2863550B2 (ja) 1999-03-03
EP0401687A3 (de) 1993-01-27
KR910001934A (ko) 1991-01-31
EP0401687B1 (de) 1997-08-06

Similar Documents

Publication Publication Date Title
DE69031197D1 (de) Plazierungs-Optimierungsverfahren /-vorrichtung für den Entwurf von Halbleiterbausteinen
DE69030231D1 (de) Vorrichtung für Halbleiterlithographie
KR880701023A (ko) 반도체 장치 제조 방법
KR880004552A (ko) 반도체장치 제조방법
DE69029630D1 (de) Mehrfach umhüllte Halbleiteranordnung und Herstellungsverfahren dafür
KR880701457A (ko) 반도체 장치 제조 방법
DE69300284T2 (de) Vorrichtung für reproduzierbare Ausrichtung von Halbleiter-Scheibe.
KR880701837A (ko) 밸브장치
DE69033794D1 (de) Halbleiteranordnung
KR880701017A (ko) 반도체 장치
DE69031609D1 (de) Halbleiteranordnung
KR900015282A (ko) 반도체 소자의 제조방법
DE69029687D1 (de) Dotierungsverfahren für Halbleiterbauelemente
KR900012355A (ko) 반도체장치 패키지
DE69029226D1 (de) Halbleiteranordnung
KR870009470A (ko) 반도체 장치 제조 방법
KR890004438A (ko) 반도체 장치
KR890005864A (ko) 반도체 장치
DE69025825D1 (de) Halbleiteranordnung
DE69027586D1 (de) Halbleiteranordnung
KR900019159A (ko) 반도체장치 제조방법
DE68929131D1 (de) LSI-Halbleiteranordnung
KR910008837A (ko) 반도체 장치의 밀봉방법
KR900015287A (ko) 반도체장치
KR900012356A (ko) 반도체장치

Legal Events

Date Code Title Description
8332 No legal effect for de